co

- cache miss
- cache eviction
- fully associative cache (only tag and offset)
- set associative cache
- cpu cache (calculate cpu cache)
- direct mapped cache

Author: xy-241

content/NUS/CS2100 Computer Organisation.md

@@ -8,7 +8,7 @@ tags:
   - computer_organisation
   - boolean_algebra
 Creation Date: 2024-02-12, 18:18
-Last Date: 2024-11-09T11:18:29+08:00
+Last Date: 2024-11-09T17:29:51+08:00
 References: 
 draft: 
 description: Find notes and cheat sheets for NUS CS2100 on this website. Get help preparing for your final exam and answers to your questions.
@@ -199,4 +199,6 @@ title: cs2100 nus notes
 - [ ] [[Cache Miss]]
 - [ ] [[Cache Strategy]]
 - [ ] [[Direct Mapped Cache]]
-- [ ] [[Set Associative Cache]]
+- [ ] [[Set Associative Cache]]
+- [ ] [[Fully Associative Cache]]
+- [ ] [[Cache Eviction]]

content/OS/CPU/CPU Cache.md

@@ -6,13 +6,21 @@ Author Profile:
 tags:
   - OS
 Creation Date: 2023-07-14T20:41:40+08:00
-Last Date: 2024-11-09T10:50:16+08:00
+Last Date: 2024-11-09T21:02:36+08:00
 References: 
 ---
 ## Abstract
 ---
 - A **small-sized** type of volatile computer memory that provides **high-speed data access** to a [[CPU]]. **10-100 times faster** than accessing accessing data from [[Main Memory]]. Built with [[Main Memory#SRAM]]
 
+
+>[!important] CPU Cache size calculation
+> [[Direct Mapped Cache]]: Cache size = (Number of cache blocks) × (Block size)
+> 
+> [[Set Associative Cache]]: Cache size = (Number of sets) × (Associativity) × (Block size)
+> 
+> [[Fully Associative Cache]]: Cache size = (Number of cache blocks) × (Block size)
+
 >[!question] Differences between L1, L2, and L3 CPU Cache?
 > **L1 Cache** is known as **primary cache**, runs at the **same speed** as the **CPU**.
 > 

content/OS/CPU/Cache Miss.md

@@ -6,7 +6,7 @@ Author Profile:
 tags:
   - computer_organisation
 Creation Date: 2024-11-06, 16:30
-Last Date: 2024-11-09T11:39:02+08:00
+Last Date: 2024-11-09T17:22:00+08:00
 References: 
 draft: 
 description: 
@@ -16,6 +16,11 @@ description:
 - When the [[CPU]] requests data that is not found in the [[CPU Cache]]
 - It requires fetching the data from the slower [[Main Memory]], incurring a higher access time compared to a [[Cache Locality#Cache Hit]]
 
+>[!important]
+> The total miss is the sum of [[#Compulsory Miss]], [[#Conflict Miss]] and [[#Capacity Miss]].
+> 
+> Capacity miss is the **total miss excluding cold miss**, when **conflict miss is zero**. So capacity miss only happens on [[Fully Associative Cache]].
+
 ### Compulsory Miss
 - Also known as **cold start miss** or **first reference miss**
 - First time accessing the data
@@ -27,9 +32,16 @@ description:
 >[!important]
 > This can be reduced with [[Set Associative Cache]]. A [[Direct Mapped Cache]] of size $N$ has about the same miss rate as a [[Set Associative Cache|2-way set associative cache]] of size $N/2$.
 
+>[!important]
+> For the same cache size, **conflict miss goes down** with **increasing associativity**. Conflict miss is $0$ for [[Fully Associative Cache]].
+
+
 ### Capacity Miss
 - When data is discarded from [[CPU Cache]] as the cpu cache is running out of space 
 
+>[!important]
+> For the **same cache size**, capacity miss **remains the same irrespective of associativity**. **Capacity miss decreases** with **increasing cache size**.
+
 ## Cache Write Miss
 ---
 - The data isn't in the [[CPU Cache]] when we want to write data back

content/OS/CPU/Direct Mapped Cache.md

@@ -6,7 +6,7 @@ Author Profile:
 tags:
   - computer_organisation
 Creation Date: 2024-11-09, 10:49
-Last Date: 2024-11-09T15:41:27+08:00
+Last Date: 2024-11-09T20:56:18+08:00
 References: 
 draft: 
 description: 
@@ -17,6 +17,10 @@ description:
 +-----------------------------------------------------------+
 |                        32-bit Address                     |
 +-----------------------+------------+----------+-----------+
+|                 Block              |        Offset        |
+|                 Number             |                      |
+|               (28 bits)            |       (4 bits)       |
++-----------------------+------------+----------+-----------+
 |         Cache         |   Cache    |   Word   |    Byte   |
 |          Tag          |   Index    |  Offset  |   Offset  |
 |        (18 bits)      | (10 bits)  | (2 bits) |  (2 bits) |
@@ -32,5 +36,3 @@ description:
 > 1. We first use the **cache index to locate the cache line**
 > 2. We use the **valid bit** to check if the cache line contains data. If it does, and the **tag matches the given address**, we can select the word needed using the **word offset** with a help of a [[Multiplexer]]
 > 3. Otherwise, there is a cache miss.
-
-

content/OS/CPU/Fully Associative Cache.md

@@ -0,0 +1,24 @@
+---
+Author:
+  - Xinyang YU
+Author Profile:
+  - https://linkedin.com/in/xinyang-yu
+tags:
+  - computer_organisation
+Creation Date: 2024-11-09, 16:54
+Last Date: 2024-11-09T20:55:35+08:00
+References: 
+draft: 
+description: 
+---
+## Abstract
+---
+![[fully_associative_cache_circuitry.png]]
+
+- In a fully associative cache, a [[CPU Cache#Cache Line|cache line]] is not restricted by a cache index or cache set index and can be placed in any location. However, **memory access requires searching all cache lines**
+
+>[!important]
+> This approach is **beneficial for very small caches**, as it eliminates [[Cache Miss#Conflict Miss|conflict misses]] by allowing data to reside anywhere within the cache, but it takes a lot more resources to locate the cache.
+
+>[!important] Just consists of 2 parts
+> Since each cache line isn't restricted to a certain group of memory addresses, there is no cache set index or cache index. Therefore, the **block number is the same as the tag number for a fully associative cache**.

content/OS/CPU/Set Associative Cache.md

@@ -6,7 +6,7 @@ Author Profile:
 tags:
   - computer_organisation
 Creation Date: 2024-11-09, 10:52
-Last Date: 2024-11-09T15:55:20+08:00
+Last Date: 2024-11-09T20:51:44+08:00
 References: 
 draft: 
 description: 
@@ -17,6 +17,10 @@ description:
 +-----------------------------------------------------------+
 |                        32-bit Address                     |
 +-----------------------+------------+----------+-----------+
+|                 Block              |        Offset        |
+|                 Number             |                      |
+|               (29 bits)            |       (3 bits)       |
++-----------------------+------------+----------+-----------+
 |         Cache         |    Set     |   Word   |    Byte   |
 |          Tag          |   Index    |  Offset  |   Offset  |
 |        (28 bits)      |  (1 bits)  | (1 bits) |  (2 bits) |

content/OS/CPU/assets/fully_associative_cache_circuitry.png

@@ -5,8 +5,9 @@ Author Profile:
   - https://linkedin.com/in/xinyang-yu
 tags:
   - system_design
+  - computer_organisation
 Creation Date: 2024-11-06, 17:17
-Last Date: 2024-11-06T17:18:26+08:00
+Last Date: 2024-11-09T17:44:21+08:00
 References: 
 draft: 
 description: 
@@ -16,9 +17,12 @@ description:
 - Once the [[Cache Server]] is full, any requests to add items to the cache server might cause existing items to be **removed**
 - Can be handled gracefully with [[#Eviction Policy]]
 
+>[!important] CPU Cache 
+> In both [[Set Associative Cache|set-associative]] and [[Fully Associative Cache|fully associative caches]], an [[#Eviction Policy|eviction policy]] is necessary to determine which [[CPU Cache#Cache Line|cache line]] to replace when a new line needs to be loaded. This is because **multiple memory addresses can map to the same set of cache lines**. In contrast, a [[Direct Mapped Cache|direct-mapped cache]] has a **one-to-one mapping between memory addresses and cache lines**. Therefore, when a new line needs to be loaded, the existing line at that specific location is simply replaced.
+
 ### Eviction Policy
 - Strategies to handle [[Cache Eviction]]
-- One common strategy is [[LRU]]
+- One common strategy is [[LRU]] which takes advantage of [[Cache Locality#Temporal Locality]]
 
 >[!important] Other common policies
 > **First in first out (FIFO)**