co

- cache miss (handle conflict miss)
- direct mapped cache
- set associative cache

Author: xy-241

content/NUS/CS2100 Computer Organisation.md

@@ -8,7 +8,7 @@ tags:
   - computer_organisation
   - boolean_algebra
 Creation Date: 2024-02-12, 18:18
-Last Date: 2024-11-06T17:19:42+08:00
+Last Date: 2024-11-09T11:18:29+08:00
 References: 
 draft: 
 description: Find notes and cheat sheets for NUS CS2100 on this website. Get help preparing for your final exam and answers to your questions.
@@ -194,7 +194,9 @@ title: cs2100 nus notes
 
 ## Week 12
 ---
-- [ ] [[CPU Cache]]
 - [ ] [[Cache Locality]]
+- [ ] [[CPU Cache]]
 - [ ] [[Cache Miss]]
-- [ ] [[Cache Strategy]]
+- [ ] [[Cache Strategy]]
+- [ ] [[Direct Mapped Cache]]
+- [ ] [[Set Associative Cache]]

content/OS/CPU/CPU Cache.md

@@ -6,7 +6,7 @@ Author Profile:
 tags:
   - OS
 Creation Date: 2023-07-14T20:41:40+08:00
-Last Date: 2024-11-06T16:27:29+08:00
+Last Date: 2024-11-09T10:50:16+08:00
 References: 
 ---
 ## Abstract
@@ -26,28 +26,16 @@ References:
 >[!important] Spatial locality
 > A cache line typically contains one or more [[Computer Data Representation#Word|words]]. When the CPU fetches data from memory, it retrieves an entire cache line, not just the specific bytes needed immediately. This takes advantage of [[Cache Locality#Spacial Locality|spatial locality]].
 
-### CPU Cache and Cache Line Internals
-
-```
-+-----------------------------------------------------------+
-|                        32-bit Address                     |
-+-----------------------+------------+----------+-----------+
-|         Cache         |   Cache    |   Word   |    Byte   |
-|          Tag          |   Index    |  Offset  |   Offset  |
-|        (18 bits)      | (10 bits)  | (2 bits) |  (2 bits) |
-+-----------------------+------------+----------+-----------+
- ```
-
-- In the above example, the [[CPU Cache]] has $2^{10}$ [[#Cache Line]], each contains $2^2$ words, each [[Computer Data Representation#Word|word]] is $2^2$ bytes 
-- Each cache line is indexed with a **cache index**. This allows a CPU cache with limited storage to cover the entire main memory because **multiple physical addresses can map to the same cache line**. However, this mapping also means that multiple physical addresses share the same cache line. To **distinguish between these different addresses**, each cache line includes a **cache tag** that **identifies the specific physical address** currently stored in that line
-
->[!question] How is cache line updated?
-> ![[cpu_cache_cache_line.png|600]]
+>[!question] How big should a cache line be?
+> ![[cache_line_size.png]]
 > 
-> 1. We first use the **cache index to locate the cache line**
-> 2. We use the **valid bit** to check if the cache line contains data. If it does, and the **tag matches the given address**, we can select the word needed using the **word offset** with a help of a [[Multiplexer]]
-> 3. Otherwise, there is a cache miss.
-
+> The **larger the cache line**, the better we can **take advantage of spatial localit**y, since we have more surrounding data cached in the cpu cache.
+> 
+> However, this brings a **larger miss penalty**, as it **takes longer to transfer** one cache line to the CPU cache.
+> 
+> Furthermore, CPU cache has a **very limited size**. The larger the cache line, the **fewer cache lines** can be loaded into the CPU cache. Consequently, the cached data tends to be more concentrated, and the **miss rate will increase**.
+> 
+> Therefore, we need to find a **sweet spot in the cache line size** to **maximise spatial locality** and **reduce the miss penalty and miss rate**.
 
 
 

content/OS/CPU/Cache Miss.md

@@ -6,7 +6,7 @@ Author Profile:
 tags:
   - computer_organisation
 Creation Date: 2024-11-06, 16:30
-Last Date: 2024-11-06T17:42:43+08:00
+Last Date: 2024-11-09T11:39:02+08:00
 References: 
 draft: 
 description: 
@@ -24,6 +24,9 @@ description:
 - Also known as **collision miss** or **interference miss**
 - When multiple data mapped to the same [[CPU Cache#Cache Line]]
 
+>[!important]
+> This can be reduced with [[Set Associative Cache]]. A [[Direct Mapped Cache]] of size $N$ has about the same miss rate as a [[Set Associative Cache|2-way set associative cache]] of size $N/2$.
+
 ### Capacity Miss
 - When data is discarded from [[CPU Cache]] as the cpu cache is running out of space 
 

content/OS/CPU/Direct Mapped Cache.md

@@ -0,0 +1,36 @@
+---
+Author:
+  - Xinyang YU
+Author Profile:
+  - https://linkedin.com/in/xinyang-yu
+tags:
+  - computer_organisation
+Creation Date: 2024-11-09, 10:49
+Last Date: 2024-11-09T15:41:27+08:00
+References: 
+draft: 
+description: 
+---
+## Abstract
+---
+```
++-----------------------------------------------------------+
+|                        32-bit Address                     |
++-----------------------+------------+----------+-----------+
+|         Cache         |   Cache    |   Word   |    Byte   |
+|          Tag          |   Index    |  Offset  |   Offset  |
+|        (18 bits)      | (10 bits)  | (2 bits) |  (2 bits) |
++-----------------------+------------+----------+-----------+
+ ```
+
+- In the above example, the [[CPU Cache]] has $2^{10}$ [[#Cache Line]], each contains $2^2$ words, each [[Computer Data Representation#Word|word]] is $2^2$ bytes 
+- Each cache line is indexed with a **cache index**. This allows a CPU cache with limited storage to cover the entire main memory because **multiple physical addresses can map to the same cache line**. However, this mapping also means that multiple physical addresses share the same cache line. To **distinguish between these different addresses**, each cache line includes a **cache tag** that **identifies the specific physical address** currently stored in that line
+
+>[!question] How is data read?
+> ![[cpu_cache_cache_line.png|600]]
+> 
+> 1. We first use the **cache index to locate the cache line**
+> 2. We use the **valid bit** to check if the cache line contains data. If it does, and the **tag matches the given address**, we can select the word needed using the **word offset** with a help of a [[Multiplexer]]
+> 3. Otherwise, there is a cache miss.
+
+

content/OS/CPU/Set Associative Cache.md

@@ -0,0 +1,40 @@
+---
+Author:
+  - Xinyang YU
+Author Profile:
+  - https://linkedin.com/in/xinyang-yu
+tags:
+  - computer_organisation
+Creation Date: 2024-11-09, 10:52
+Last Date: 2024-11-09T15:55:20+08:00
+References: 
+draft: 
+description: 
+---
+## Abstract
+---
+```
++-----------------------------------------------------------+
+|                        32-bit Address                     |
++-----------------------+------------+----------+-----------+
+|         Cache         |    Set     |   Word   |    Byte   |
+|          Tag          |   Index    |  Offset  |   Offset  |
+|        (28 bits)      |  (1 bits)  | (1 bits) |  (2 bits) |
++-----------------------+------------+----------+-----------+
+ ```
+
+- One way to design a [[CPU Cache|CPU cache]] is to have it consist of a number of sets, each containing $n$ [[CPU Cache#Cache Line|cache lines]]. Within a set, a memory block can be placed in any of the $n$ cache lines.
+- In the above example, we have a 2-way set associative cache. The [[CPU Cache]] has $2^{1}$ sets, each containing $2$ cache lines. Each contains $2^{1}$ words, and each [[Computer Data Representation#Word|word]] is $2^2$ bytes 
+
+>[!question] What is the benefit?
+> ![[2-way_set_associative_cache.png]]
+> 
+> Set associative caches reduce the likelihood of [[Cache Miss#Conflict Miss|conflict misses]] compared to [[Direct Mapped Cache|direct-mapped caches]]. In a direct-mapped cache, if two **frequently accessed memory locations map to the same cache index, they will constantly evict each other,** causing repeated conflict misses. A set associative cache provides multiple cache lines within each set, allowing these memory locations to **coexist in the cache simultaneously**, minimising conflict misses and improving performance.
+
+
+>[!question] How is data read?
+> ![[set_associative_cache_read_circuit.png|600]]
+> 
+> 1. We first use the **set index to locate the set**
+> 2. We simultaneously "search" on all **valid bit** and **tags** of the set to check if one of the cache line contains data. If it does, and the **tag matches the given address**, we can select the word needed using with a help of a [[Multiplexer]]
+> 3. Otherwise, there is a cache miss.