Tentative support for avx512f extensions to 256 bit registers#1345
Tentative support for avx512f extensions to 256 bit registers#1345serge-sans-paille wants to merge 1 commit into
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In addition to missing instructions (e.g. bas on int64_t etc) this mostly changes the mask representation from vector register to scalar, thus the big diff.
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Are we sure that we only need avx512f for this? It seems to me that instructions like https://diamondinoia.com/simdref/#_mm256_cmp_epi32_mask requires avx512f + VL. Let me know where I am wrong. Cheers, |
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You're right, all of this requires avx512f+avx512vl. It turns out most build have both (see https://en.wikipedia.org/wiki/AVX-512#CPUs_with_AVX-512) but we currently don't have anything to model avx512vl, which should be the parent of avx512f_256. |
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I guess it might be called avx512vl_256 at that point as we will also have avx512vl_128. What do you think? I agree, most CPU have 512+extensions. |
It looks like avx512vl does not have any 512bit instruction :-) but it still has avx512 in its name and it implies avx512f, so I agree with you. |
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Actually, my suggestion might be wrong: https://diamondinoia.com/simdref/#_mm_maskz_andnot_pd There are instructions that require DQ + VL for example. |
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In addition to missing instructions (e.g. bas on int64_t etc) this mostly changes the mask representation from vector register to scalar, thus the big diff.