Add Agilex 5 FCS and wolfBoot integration - #846
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Pull request overview
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Adds an Altera Agilex 5 (013B) port and integration points to boot wolfBoot as BL33 in the GSRD SD-card flow, including SDHCI/platform init, memory mapping, example FIT artifacts, and CI build coverage.
Changes:
- Adds Agilex 5 HAL (C + header), linker script, FIT example, and a BL33 smoke-test app.
- Updates AArch64 startup/MMU mappings and SDHCI behavior to support Agilex 5 boot/SD timing.
- Updates disk-boot logging and adds docs/config + GitHub Actions build coverage for the new target.
Reviewed changes
Copilot reviewed 16 out of 16 changed files in this pull request and generated 7 comments.
Show a summary per file
| File | Description |
|---|---|
| test-app/app_agilex5.c | Adds a BL33 smoke-test app for Agilex 5 (timer + EL print). |
| src/update_disk.c | Improves disk-boot debug output (block size + pointer-format prints). |
| src/sdhci.c | Adds command-line reset, inhibit timeouts, optional post-command delay, and CMD8 retry logic. |
| src/boot_aarch64_start.S | Adds Agilex 5 include, adjusts CNTFRQ/RVBAR handling, and adds Agilex 5 MMU mappings. |
| src/boot_aarch64.c | Adds Agilex 5 HAL include selection for AArch64 boot code. |
| include/sdhci.h | Adds reset bit definitions and new SDHCI tuning/behavior macros. |
| hal/agilex5.ld | New linker script matching BL33 placement at 0x80200000. |
| hal/agilex5.its | Example FIT description for Agilex 5 Linux payload (kernel + DTB). |
| hal/agilex5.h | New Agilex 5 target configuration and platform constants. |
| hal/agilex5.c | New Agilex 5 HAL implementation (timer, UART, DT fixups, SDHCI PHY + DMA cache ops). |
| docs/Targets.md | Documents the new Agilex 5 target and references Agilex5 bring-up doc. |
| docs/Agilex5.md | Adds bring-up and integration documentation (GSRD/FIT/WIC/test order/CI). |
| config/examples/agilex5_013b_sdcard.config | Adds a buildable example config for Agilex 5 SD-card boot flow. |
| arch.mk | Adds Agilex 5 AArch64 flags + target-specific bootloader responsibilities. |
| .github/workflows/test-configs.yml | Adds Agilex 5 config to existing CI matrix via reusable workflow. |
| .github/workflows/test-build-agilex5.yml | Adds a dedicated Agilex 5 build workflow (path-filtered). |
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| hal_init(); | ||
| wolfBoot_printf("\nAgilex 5 BL33 smoke test\n"); | ||
| wolfBoot_printf("Current EL: %d (expected 2)\n", current_el()); |
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| wolfBoot_printf("Generic timer advanced by %d us\n", | ||
| (uint32_t)(now - start)); |
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| /* Choose partition with higher version */ | ||
| selected = (pB_ver_u > pA_ver_u) ? 1 : 0; | ||
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| #ifdef WOLFBOOT_FSP |
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| int sdhci_cmd(uint32_t cmd_index, uint32_t cmd_arg, uint8_t resp_type) | ||
| { | ||
| /* send command */ |
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| for (addr = start; addr < end; addr += CACHE_LINE_SIZE) { | ||
| if (is_write != 0) | ||
| __asm__ volatile("dc cvac, %0" : : "r"(addr) : "memory"); | ||
| else | ||
| __asm__ volatile("dc civac, %0" : : "r"(addr) : "memory"); | ||
| } |
| SDM -> U-Boot SPL -> TF-A BL31/EL3 -> wolfBoot BL33/EL2 -> signed Linux FIT | ||
| ``` | ||
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| SPL remains responsible for DDR, clocks, resets, pinmux, the SD6HC PHY and |
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| #if defined(TARGET_versal) || defined(TARGET_agilex5) | ||
| /* Versal: RVBAR is handled by PLM, not accessible from APU in JTAG mode */ | ||
| /* Cortex-A72 timestamp clock frequency (from Versal HW) */ | ||
| /* BL31 has already programmed CNTFRQ_EL0 on BL33-entry platforms. */ | ||
| .set counterfreq, 100000000 |
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Description
partner pr: wolfSSL/meta-wolfssl#177