Remove ipin rr switch

libs/librrgraph/src/io/rr_graph_reader.cpp

@@ -66,8 +66,6 @@ void load_rr_file(RRGraphBuilder* rr_graph_builder,
                   const t_arch* arch,
                   t_chan_width* chan_width,
                   const e_base_cost_type base_cost_type,
-                  RRSwitchId* wire_to_rr_ipin_switch,
-                  int* wire_to_rr_ipin_switch_between_dice,
                   const char* read_rr_graph_name,
                   std::string* loaded_rr_graph_filename,
                   bool read_edge_metadata,
@@ -86,8 +84,6 @@ void load_rr_file(RRGraphBuilder* rr_graph_builder,
     RrGraphSerializer reader(
         graph_type,
         base_cost_type,
-        wire_to_rr_ipin_switch,
-        wire_to_rr_ipin_switch_between_dice,
         do_check_rr_graph,
         read_rr_graph_name,
         loaded_rr_graph_filename,

libs/librrgraph/src/io/rr_graph_reader.h

@@ -23,8 +23,6 @@ void load_rr_file(RRGraphBuilder* rr_graph_builder,
                   const t_arch* arch,
                   t_chan_width* chan_width,
                   const e_base_cost_type base_cost_type,
-                  RRSwitchId* wire_to_rr_ipin_switch,
-                  int* wire_to_rr_ipin_switch_between_dice,
                   const char* read_rr_graph_name,
                   std::string* loaded_rr_graph_filename,
                   bool read_edge_metadata,

libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h

@@ -274,8 +274,6 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
     RrGraphSerializer(
         const e_graph_type graph_type,
         const enum e_base_cost_type base_cost_type,
-        RRSwitchId* wire_to_rr_ipin_switch,
-        int* wire_to_rr_ipin_switch_between_dice,
         bool do_check_rr_graph,
         const char* read_rr_graph_name,
         std::string* loaded_rr_graph_filename,
@@ -297,9 +295,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
         MetadataStorage<std::tuple<int, int, short>>* rr_edge_metadata,
         vtr::string_internment* strings,
         bool is_flat)
-        : wire_to_rr_ipin_switch_(wire_to_rr_ipin_switch)
-        , wire_to_rr_ipin_switch_between_dice_(wire_to_rr_ipin_switch_between_dice)
-        , chan_width_(chan_width)
+        : chan_width_(chan_width)
         , rr_nodes_(rr_nodes)
         , rr_graph_builder_(rr_graph_builder)
         , rr_graph_(rr_graph)
@@ -1147,20 +1143,6 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
         return nullptr;
     }
     inline void finish_rr_graph_rr_edges(void*& /*ctx*/) final {
-        /*initialize a vector that keeps track of the number of wire to ipin switches
-         * There should be only one wire to ipin switch. In case there are more, make sure to
-         * store the most frequent switch */
-        const auto& rr_graph = (*rr_graph_);
-        std::vector<int> count_for_wire_to_ipin_switches;
-        count_for_wire_to_ipin_switches.resize(rr_switch_inf_->size(), 0);
-        //switch for same layer Track to IPIN connection
-        //first is index, second is count
-        std::pair<int, int> most_frequent_switch(-1, 0);
-        //switch for different layer Track to IPIN connection
-        std::vector<int> count_for_wire_to_ipin_switches_between_dice;
-        count_for_wire_to_ipin_switches_between_dice.resize(rr_switch_inf_->size(), 0);
-        std::pair<int,int> most_frequent_switch_between_dice(-1,0);
-
         // Partition the rr graph edges for efficient access to
         // configurable/non-configurable edge subsets. Must be done after RR
         // switches have been allocated.
@@ -1183,36 +1165,8 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
                         "switch_id %zu is larger than num_rr_switches %zu",
                         switch_id, rr_switch_inf_->size());
                 }
-                auto node = (*rr_nodes_)[source_node];
-
-                /*Keeps track of the number of the specific type of switch that connects a wire to an ipin
-                 * use the pair data structure to keep the maximum*/
-                if (rr_graph.node_type(node.id()) == e_rr_type::CHANX || rr_graph.node_type(node.id()) == e_rr_type::CHANY) {
-                    if(rr_graph.node_type(RRNodeId(sink_node)) == e_rr_type::IPIN){
-                        if (rr_graph.node_layer_low(RRNodeId(sink_node)) == rr_graph.node_layer_low(RRNodeId(source_node))) {
-                            count_for_wire_to_ipin_switches[switch_id]++;
-                            if (count_for_wire_to_ipin_switches[switch_id] > most_frequent_switch.second) {
-                                most_frequent_switch.first = switch_id;
-                                most_frequent_switch.second = count_for_wire_to_ipin_switches[switch_id];
-                            }
-                        } else{
-                            VTR_ASSERT(rr_graph.node_layer_low(RRNodeId(sink_node)) != rr_graph.node_layer_low(RRNodeId(source_node)));
-                            count_for_wire_to_ipin_switches_between_dice[switch_id]++;
-                            if(count_for_wire_to_ipin_switches_between_dice[switch_id] > most_frequent_switch_between_dice.second){
-                                most_frequent_switch_between_dice.first = switch_id;
-                                most_frequent_switch_between_dice.second = count_for_wire_to_ipin_switches_between_dice[switch_id];
-                            }
-                        }
-                    }
-                }
             }
         }
-
-        VTR_ASSERT(wire_to_rr_ipin_switch_ != nullptr);
-        *wire_to_rr_ipin_switch_ = (RRSwitchId)most_frequent_switch.first;
-
-        VTR_ASSERT(wire_to_rr_ipin_switch_between_dice_ != nullptr);
-        *wire_to_rr_ipin_switch_between_dice_ = most_frequent_switch_between_dice.first;
     }
 
     inline EdgeWalker get_rr_graph_rr_edges(void*& /*ctx*/) final {
@@ -1844,7 +1798,6 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
             segment_inf_y_,
             segment_inf_z_,
             *rr_indexed_data_,
-            *wire_to_rr_ipin_switch_,
             base_cost_type_,
             echo_enabled_,
             echo_file_name_);
@@ -2194,8 +2147,6 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
     std::array<uxsd::enum_loc_side, 16> side_map_;
 
     // Output for loads, and constant data for writes.
-    RRSwitchId* wire_to_rr_ipin_switch_;
-    int* wire_to_rr_ipin_switch_between_dice_;
     t_chan_width* chan_width_;
     t_rr_graph_storage* rr_nodes_;
     RRGraphBuilder* rr_graph_builder_;

libs/librrgraph/src/io/rr_graph_writer.cpp

@@ -42,8 +42,6 @@ void write_rr_graph(RRGraphBuilder* rr_graph_builder,
     RrGraphSerializer reader(
         /*graph_type=*/e_graph_type(),
         /*base_cost_type=*/e_base_cost_type(),
-        /*wire_to_rr_ipin_switch=*/nullptr,
-        /*wire_to_rr_ipin_switch_between_dice=*/nullptr,
         /*do_check_rr_graph=*/false,
         /*read_rr_graph_name=*/nullptr,
         /*read_rr_graph_filename=*/nullptr,

libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp

@@ -30,7 +30,6 @@ static void load_rr_indexed_data_base_costs(const RRGraphView& rr_graph,
 static float get_delay_normalization_fac(const vtr::vector<RRIndexedDataId, t_rr_indexed_data>& rr_indexed_data, const bool echo_enabled, const char* echo_file_name);
 
 static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph,
-                                          const RRSwitchId wire_to_ipin_switch,
                                           vtr::vector<RRIndexedDataId, t_rr_indexed_data>& rr_indexed_data);
 
 /**
@@ -87,7 +86,6 @@ void alloc_and_load_rr_indexed_data(const RRGraphView& rr_graph,
                                     const std::vector<t_segment_inf>& segment_inf_y,
                                     const std::vector<t_segment_inf>& segment_inf_z,
                                     vtr::vector<RRIndexedDataId, t_rr_indexed_data>& rr_indexed_data,
-                                    const RRSwitchId wire_to_ipin_switch,
                                     e_base_cost_type base_cost_type,
                                     const bool echo_enabled,
                                     const char* echo_file_name) {
@@ -158,9 +156,7 @@ void alloc_and_load_rr_indexed_data(const RRGraphView& rr_graph,
         rr_indexed_data[index].seg_index = seg_ptr->seg_index;
     }
 
-    load_rr_indexed_data_T_values(rr_graph,
-                 wire_to_ipin_switch,
-                 rr_indexed_data);
+    load_rr_indexed_data_T_values(rr_graph, rr_indexed_data);
 
     fixup_rr_indexed_data_T_values(rr_indexed_data, total_num_segment);
 
@@ -515,7 +511,6 @@ static float get_delay_normalization_fac(const vtr::vector<RRIndexedDataId, t_rr
  *      - Placement Delay Matrix computation
  */
 static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph,
-                                          const RRSwitchId wire_to_ipin_switch,
                                           vtr::vector<RRIndexedDataId, t_rr_indexed_data>& rr_indexed_data) {
     vtr::vector<RRNodeId, std::vector<RREdgeId>> fan_in_list = get_fan_in_list(rr_graph);
 
@@ -617,8 +612,7 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph,
     {
         if (ipin_switch_count == 0) {
             VTR_LOG_WARN("No IPIN switches found. Setting T_linear to 0\n");
-            float default_ipin_switch_T_del = rr_graph.rr_switch_inf(RRSwitchId(wire_to_ipin_switch)).Tdel;
-            rr_indexed_data[RRIndexedDataId(IPIN_COST_INDEX)].T_linear = default_ipin_switch_T_del;
+            rr_indexed_data[RRIndexedDataId(IPIN_COST_INDEX)].T_linear = 0.0;
         } else {
             float average_ipin_switch_T_del = ipin_switch_T_total / ipin_switch_count;
             rr_indexed_data[RRIndexedDataId(IPIN_COST_INDEX)].T_linear = average_ipin_switch_T_del;

libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.h

@@ -12,7 +12,6 @@ void alloc_and_load_rr_indexed_data(const RRGraphView& rr_graph,
                                     const std::vector<t_segment_inf>& segment_inf_y,
                                     const std::vector<t_segment_inf>& segment_inf_z,
                                     vtr::vector<RRIndexedDataId, t_rr_indexed_data>& rr_indexed_data,
-                                    const RRSwitchId wire_to_ipin_switch,
                                     e_base_cost_type base_cost_type,
                                     const bool echo_enabled,
                                     const char* echo_file_name);

vpr/src/base/stats.cpp

@@ -69,7 +69,6 @@ void routing_stats(const Netlist<>& net_list,
                    float R_minW_pmos,
                    float grid_logic_tile_area,
                    e_directionality directionality,
-                   RRSwitchId wire_to_ipin_switch,
                    bool is_flat) {
     const DeviceContext& device_ctx = g_vpr_ctx.device();
     auto& rr_graph = device_ctx.rr_graph;
@@ -116,8 +115,12 @@ void routing_stats(const Netlist<>& net_list,
     VTR_LOG("\tTotal used logic block area: %g\n", used_area);
 
     if (route_type == e_route_type::DETAILED) {
-        count_routing_transistors(directionality, num_rr_switch, wire_to_ipin_switch,
-                                  segment_inf, R_minW_nmos, R_minW_pmos, is_flat);
+        count_routing_transistors(directionality,
+                                  num_rr_switch,
+                                  segment_inf,
+                                  R_minW_nmos,
+                                  R_minW_pmos,
+                                  is_flat);
         get_segment_usage_stats(segment_inf);
     }
 

vpr/src/base/stats.h

@@ -21,7 +21,6 @@ void routing_stats(const Netlist<>& net_list,
                    float R_minW_pmos,
                    float grid_logic_tile_area,
                    e_directionality directionality,
-                   RRSwitchId wire_to_ipin_switch,
                    bool is_flat);
 
 void print_wirelen_prob_dist(bool is_flat);

vpr/src/base/vpr_api.cpp

@@ -1500,7 +1500,6 @@ void vpr_analysis(const Netlist<>& net_list,
                   vpr_setup.RoutingArch.R_minW_pmos,
                   Arch.grid_logic_tile_area,
                   vpr_setup.RoutingArch.directionality,
-                  vpr_setup.RoutingArch.wire_to_rr_ipin_switch,
                   is_flat);
 
     if (vpr_setup.TimingEnabled) {

vpr/src/base/vpr_types.h

@@ -1493,14 +1493,6 @@ struct t_det_routing_arch {
     /// wires from another die to ipins in different die
     int wire_to_arch_ipin_switch_between_dice = -1;
 
-    /// keeps track of the type of RR graph switch
-    /// that connects wires to ipins in the RR graph
-    RRSwitchId wire_to_rr_ipin_switch;
-
-    /// keeps track of the type of RR graph switch that connects wires
-    /// from another die to ipins in different die in the RR graph
-    int wire_to_rr_ipin_switch_between_dice = -1;
-
     /// Resistance (in Ohms) of a minimum width nmos transistor.
     /// Used only in the FPGA area model.
     float R_minW_nmos;

vpr/src/power/power.cpp

@@ -979,7 +979,8 @@ static void power_usage_routing(t_power_usage* power_usage,
                 connectionbox_fanout = 0;
                 switchbox_fanout = 0;
                 for (t_edge_size iedge = 0; iedge < rr_graph.num_edges(rr_id); iedge++) {
-                    if ((RRSwitchId)rr_graph.edge_switch(rr_id, iedge) == routing_arch.wire_to_rr_ipin_switch) {
+                    RRNodeId edge_sink = rr_graph.edge_sink_node(rr_id, iedge);
+                    if (rr_graph.node_type(edge_sink) == e_rr_type::IPIN) {
                         connectionbox_fanout++;
                     } else if (rr_graph.edge_switch(rr_id, iedge) == routing_arch.delayless_switch) {
                         /* Do nothing */
@@ -1225,7 +1226,8 @@ void power_routing_init(const t_det_routing_arch& routing_arch) {
             case e_rr_type::CHANX:
             case e_rr_type::CHANY:
                 for (t_edge_size iedge = 0; iedge < rr_graph.num_edges(rr_node_idx); iedge++) {
-                    if ((RRSwitchId)rr_graph.edge_switch(rr_node_idx, iedge) == routing_arch.wire_to_rr_ipin_switch) {
+                    RRNodeId edge_sink = rr_graph.edge_sink_node(rr_node_idx, iedge);
+                    if (rr_graph.node_type(edge_sink) == e_rr_type::IPIN) {
                         fanout_to_IPIN++;
                     } else if (rr_graph.edge_switch(rr_node_idx, iedge) != routing_arch.delayless_switch) {
                         fanout_to_seg++;