Remove an unsed hash functor

libs/libarchfpga/src/arch_util.cpp

@@ -545,7 +545,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
     for (size_t i = 0; i < num_annotations; i++) {
         lut_pb_type->modes[0].interconnect[0].annotations[i].clock = lut_pb_type->annotations[i].clock;
         lut_pb_type->modes[0].interconnect[0].annotations[i].input_pins = lut_pb_type->annotations[i].input_pins;
-        lut_pb_type->modes[0].interconnect[0].annotations[i].output_pins =lut_pb_type->annotations[i].output_pins;
+        lut_pb_type->modes[0].interconnect[0].annotations[i].output_pins = lut_pb_type->annotations[i].output_pins;
         lut_pb_type->modes[0].interconnect[0].annotations[i].line_num = lut_pb_type->annotations[i].line_num;
         lut_pb_type->modes[0].interconnect[0].annotations[i].format = lut_pb_type->annotations[i].format;
         lut_pb_type->modes[0].interconnect[0].annotations[i].type = lut_pb_type->annotations[i].type;

libs/libarchfpga/src/physical_types_util.cpp

@@ -155,7 +155,7 @@ static std::tuple<int, int, int, int, int> get_pin_index_for_inst(t_physical_til
         logical_block_idx = -1;
         pb_type_idx = 0;
     } else {
-        auto logical_block = get_logical_block_from_pin_physical_num(type, pin_physical_num);
+        t_logical_block_type_ptr logical_block = get_logical_block_from_pin_physical_num(type, pin_physical_num);
         auto pb_type = get_pb_pin_from_pin_physical_num(type, pin_physical_num)->parent_node->pb_type;
         VTR_ASSERT(logical_block != nullptr);
         logical_block_idx = logical_block->index;
@@ -236,10 +236,9 @@ static int get_logical_block_physical_pin_num_offset(t_physical_tile_type_ptr ph
                                                      const t_sub_tile* curr_sub_tile,
                                                      t_logical_block_type_ptr curr_logical_block,
                                                      const int curr_relative_cap) {
-    int offset;
-    offset = get_sub_tile_inst_physical_pin_num_offset(physical_tile, curr_sub_tile, curr_relative_cap);
+    int offset = get_sub_tile_inst_physical_pin_num_offset(physical_tile, curr_sub_tile, curr_relative_cap);
 
-    for (auto eq_site : curr_sub_tile->equivalent_sites) {
+    for (t_logical_block_type_ptr eq_site : curr_sub_tile->equivalent_sites) {
         if (eq_site == curr_logical_block)
             break;
         offset += (int)eq_site->pin_logical_num_to_pb_pin_mapping.size();
@@ -255,13 +254,11 @@ static int get_pin_logical_num_from_pin_physical_num(t_physical_tile_type_ptr ph
     VTR_ASSERT(sub_tile_cap != -1);
     auto logical_block = get_logical_block_from_pin_physical_num(physical_tile, physical_num);
 
-    int pin_logical_num;
-
     int offset = get_logical_block_physical_pin_num_offset(physical_tile,
                                                            sub_tile,
                                                            logical_block,
                                                            sub_tile_cap);
-    pin_logical_num = physical_num - offset;
+    int pin_logical_num = physical_num - offset;
 
     return pin_logical_num;
 }
@@ -273,7 +270,6 @@ static std::vector<int> get_pb_pin_src_pins(t_physical_tile_type_ptr physical_ty
                                             const t_pb_graph_pin* pin) {
     std::vector<int> driving_pins;
     const auto& edges = pin->input_edges;
-    t_pb_graph_pin** connected_pins_ptr;
     int num_edges = pin->num_input_edges;
     int num_pins = 0;
 
@@ -285,7 +281,7 @@ static std::vector<int> get_pb_pin_src_pins(t_physical_tile_type_ptr physical_ty
 
     for (int edge_idx = 0; edge_idx < num_edges; edge_idx++) {
         const t_pb_graph_edge* pb_graph_edge = edges[edge_idx];
-        connected_pins_ptr = pb_graph_edge->input_pins;
+        t_pb_graph_pin** connected_pins_ptr = pb_graph_edge->input_pins;
         num_pins = pb_graph_edge->num_input_pins;
 
         for (int pin_idx = 0; pin_idx < num_pins; pin_idx++) {
@@ -315,7 +311,6 @@ static std::vector<int> get_pb_pin_sink_pins(t_physical_tile_type_ptr physical_t
                                              const t_pb_graph_pin* pin) {
     std::vector<int> sink_pins;
     const auto& edges = pin->output_edges;
-    t_pb_graph_pin** connected_pins_ptr;
     int num_edges = pin->num_output_edges;
     int num_pins = 0;
 
@@ -327,7 +322,7 @@ static std::vector<int> get_pb_pin_sink_pins(t_physical_tile_type_ptr physical_t
 
     for (int edge_idx = 0; edge_idx < num_edges; edge_idx++) {
         const t_pb_graph_edge* pb_graph_edge = edges[edge_idx];
-        connected_pins_ptr = pb_graph_edge->output_pins;
+        t_pb_graph_pin** connected_pins_ptr = pb_graph_edge->output_pins;
         num_pins = pb_graph_edge->num_output_pins;
 
         for (int pin_idx = 0; pin_idx < num_pins; pin_idx++) {
@@ -392,12 +387,12 @@ static int get_num_reachable_sinks(t_physical_tile_type_ptr physical_tile,
     const auto& connected_sinks = pb_pin->connected_sinks_ptc;
 
     // If ref_sink_num is not reachable by pin_physical_num return 0
-    if (connected_sinks.find(ref_sink_num) == connected_sinks.end()) {
+    if (!connected_sinks.contains(ref_sink_num)) {
         return 0;
     }
 
     for (auto sink_num : sink_grp) {
-        if (connected_sinks.find(sink_num) != connected_sinks.end()) {
+        if (connected_sinks.contains(sink_num)) {
             num_reachable_sinks++;
         }
     }
@@ -431,7 +426,7 @@ int get_logical_block_physical_sub_tile_index(t_physical_tile_type_ptr physical_
     int sub_tile_index = ARCH_FPGA_UNDEFINED_VAL;
     for (const auto& sub_tile : physical_tile->sub_tiles) {
         auto eq_sites = sub_tile.equivalent_sites;
-        auto it = std::find(eq_sites.begin(), eq_sites.end(), logical_block);
+        auto it = std::ranges::find(eq_sites, logical_block);
         if (it != eq_sites.end()) {
             sub_tile_index = sub_tile.index;
         }
@@ -467,7 +462,7 @@ int get_logical_block_physical_sub_tile_index(t_physical_tile_type_ptr physical_
     int sub_tile_index = ARCH_FPGA_UNDEFINED_VAL;
     for (const auto& sub_tile : physical_tile->sub_tiles) {
         auto eq_sites = sub_tile.equivalent_sites;
-        auto it = std::find(eq_sites.begin(), eq_sites.end(), logical_block);
+        auto it = std::ranges::find(eq_sites, logical_block);
         if (it != eq_sites.end()
             && (sub_tile.capacity.is_in_range(sub_tile_capacity))) {
             sub_tile_index = sub_tile.index;
@@ -497,13 +492,13 @@ t_logical_block_type_ptr pick_logical_type(t_physical_tile_type_ptr physical_til
 
 bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block) {
     const auto& equivalent_tiles = logical_block->equivalent_tiles;
-    return std::find(equivalent_tiles.begin(), equivalent_tiles.end(), physical_tile) != equivalent_tiles.end();
+    return std::ranges::find(equivalent_tiles, physical_tile) != equivalent_tiles.end();
 }
 
 bool is_sub_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block, int sub_tile_loc) {
     bool capacity_compatible = false;
-    for (auto& sub_tile : physical_tile->sub_tiles) {
-        auto result = std::find(sub_tile.equivalent_sites.begin(), sub_tile.equivalent_sites.end(), logical_block);
+    for (const t_sub_tile& sub_tile : physical_tile->sub_tiles) {
+        auto result = std::ranges::find(sub_tile.equivalent_sites, logical_block);
 
         if (sub_tile.capacity.is_in_range(sub_tile_loc) && result != sub_tile.equivalent_sites.end()) {
             capacity_compatible = true;
@@ -687,18 +682,18 @@ std::vector<std::string> block_type_class_index_to_pin_names(t_physical_tile_typ
         pin_info.push_back(block_type_pin_index_to_pin_inst(type, pin_physical_num, is_flat));
     }
 
-    auto cmp = [](const t_pin_inst_port& lhs, const t_pin_inst_port& rhs) {
+    auto cmp = [](const t_pin_inst_port& lhs, const t_pin_inst_port& rhs) noexcept {
         return lhs.pin_physical_num < rhs.pin_physical_num;
     };
 
-    //Ensure all the pins are in order
-    std::sort(pin_info.begin(), pin_info.end(), cmp);
+    // Ensure all the pins are in order
+    std::ranges::sort(pin_info, cmp);
 
-    //Determine ranges for each capacity instance and port pair
+    // Determine ranges for each capacity instance and port pair
     std::map<std::tuple<int, int, int, int, int>, std::array<int, 4>> pin_ranges;
-    for (const auto& pin_inf : pin_info) {
+    for (const t_pin_inst_port& pin_inf : pin_info) {
         auto key = std::make_tuple(pin_inf.sub_tile_index, pin_inf.capacity_instance, pin_inf.logical_block_index, pin_inf.pb_type_idx, pin_inf.port_index);
-        if (!pin_ranges.count(key)) {
+        if (!pin_ranges.contains(key)) {
             pin_ranges[key][0] = pin_inf.pin_index_in_port;
             pin_ranges[key][1] = pin_inf.pin_index_in_port;
             pin_ranges[key][2] = pin_inf.pin_physical_num;
@@ -783,7 +778,7 @@ std::tuple<const t_sub_tile*, int> get_sub_tile_from_class_physical_num(t_physic
     int num_seen_class = (is_on_tile) ? 0 : (int)physical_tile->class_inf.size();
     int class_num_offset = num_seen_class;
 
-    for (auto& sub_tile : physical_tile->sub_tiles) {
+    for (const t_sub_tile& sub_tile : physical_tile->sub_tiles) {
         int sub_tile_num_class = is_on_tile ? sub_tile.class_range.total_num() : get_sub_tile_num_internal_classes(&sub_tile);
         num_seen_class += sub_tile_num_class;
 
@@ -801,8 +796,8 @@ std::tuple<const t_sub_tile*, int> get_sub_tile_from_class_physical_num(t_physic
 
 t_logical_block_type_ptr get_logical_block_from_class_physical_num(t_physical_tile_type_ptr physical_tile,
                                                                    int class_physical_num) {
-    auto pin_list = get_pin_list_from_class_physical_num(physical_tile, class_physical_num);
-    VTR_ASSERT((int)pin_list.size() != 0);
+    std::vector<int> pin_list = get_pin_list_from_class_physical_num(physical_tile, class_physical_num);
+    VTR_ASSERT(!pin_list.empty());
     return get_logical_block_from_pin_physical_num(physical_tile, pin_list[0]);
 }
 
@@ -895,7 +890,7 @@ std::tuple<const t_sub_tile*, int> get_sub_tile_from_pin_physical_num(t_physical
     int total_pin_counts = pin_on_tile ? 0 : physical_tile->num_pins;
     int pin_offset = total_pin_counts;
 
-    for (auto& sub_tile : physical_tile->sub_tiles) {
+    for (const t_sub_tile& sub_tile : physical_tile->sub_tiles) {
         int sub_tile_num_pins = pin_on_tile ? sub_tile.num_phy_pins : sub_tile.total_num_internal_pins();
         total_pin_counts += sub_tile_num_pins;
 
@@ -1269,9 +1264,7 @@ bool intra_tile_nodes_connected(t_physical_tile_type_ptr physical_type,
     } else {
         const t_pb_graph_pin* from_pb_graph_pin = get_pb_pin_from_pin_physical_num(physical_type, pin_physical_num);
 
-        auto res = from_pb_graph_pin->connected_sinks_ptc.find(sink_physical_num);
-
-        if (res == from_pb_graph_pin->connected_sinks_ptc.end()) {
+        if (!from_pb_graph_pin->connected_sinks_ptc.contains(sink_physical_num)) {
             return false;
         } else {
             return true;
@@ -1304,8 +1297,7 @@ float get_pin_primitive_comb_delay(t_physical_tile_type_ptr physical_type,
                                                                     pin_physical_num);
     VTR_ASSERT(pb_pin->is_primitive_pin());
 
-    auto it = std::max_element(pb_pin->pin_timing_del_max.begin(), pb_pin->pin_timing_del_max.end());
-
+    auto it = std::ranges::max_element(pb_pin->pin_timing_del_max);
     if (it == pb_pin->pin_timing_del_max.end()) {
         return 0.;
     } else {
@@ -1323,9 +1315,9 @@ bool classes_in_same_block(t_physical_tile_type_ptr physical_tile,
     }
 
     // Two functions are considered to be in the same group if share at least two level of blocks
-    const int NUM_SIMILAR_PB_NODE_THRESHOLD = 2;
-    auto first_class_pin_list = get_pin_list_from_class_physical_num(physical_tile, first_class_ptc_num);
-    auto second_class_pin_list = get_pin_list_from_class_physical_num(physical_tile, second_class_ptc_num);
+    constexpr int NUM_SIMILAR_PB_NODE_THRESHOLD = 2;
+    std::vector<int> first_class_pin_list = get_pin_list_from_class_physical_num(physical_tile, first_class_ptc_num);
+    std::vector<int> second_class_pin_list = get_pin_list_from_class_physical_num(physical_tile, second_class_ptc_num);
 
     auto first_pb_graph_pin = get_pb_pin_from_pin_physical_num(physical_tile, first_class_pin_list[0]);
     auto second_pb_graph_pin = get_pb_pin_from_pin_physical_num(physical_tile, second_class_pin_list[0]);
@@ -1340,7 +1332,7 @@ bool classes_in_same_block(t_physical_tile_type_ptr physical_tile,
     int num_shared_pb_graph_node = 0;
     curr_pb_graph_node = second_pb_graph_pin->parent_node;
     while (curr_pb_graph_node != nullptr) {
-        auto find_res = std::find(first_pb_graph_node_chain.begin(), first_pb_graph_node_chain.end(), curr_pb_graph_node);
+        auto find_res = std::ranges::find(first_pb_graph_node_chain, curr_pb_graph_node);
         if (find_res != first_pb_graph_node_chain.end()) {
             num_shared_pb_graph_node++;
             if (num_shared_pb_graph_node >= NUM_SIMILAR_PB_NODE_THRESHOLD)

libs/librrgraph/src/base/rr_graph_utils.cpp

@@ -180,7 +180,7 @@ void rr_set_sink_locs(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_buil
 
         // See if we have encountered this tile type/ptc combo before, and used saved offset if so
         vtr::Point<int> new_loc(-1, -1);
-        if ((physical_type_offsets.find(tile_type) != physical_type_offsets.end()) && (physical_type_offsets[tile_type].find(node_ptc) != physical_type_offsets[tile_type].end())) {
+        if (physical_type_offsets.contains(tile_type) && physical_type_offsets[tile_type].contains(node_ptc)) {
             new_loc = tile_bb.bottom_left() + physical_type_offsets[tile_type].at(node_ptc);
         } else { /* We have not seen this tile type/ptc combo before */
             // The IPINs of the current SINK node
@@ -197,7 +197,7 @@ void rr_set_sink_locs(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_buil
             std::vector<float> y_coords;
 
             // Add coordinates of each "cluster-edge" pin to vectors
-            for (const auto& pin : sink_ipins) {
+            for (const RRNodeId pin : sink_ipins) {
                 int pin_x = rr_graph.node_xlow(pin);
                 int pin_y = rr_graph.node_ylow(pin);
 
@@ -212,7 +212,7 @@ void rr_set_sink_locs(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_buil
                        (int)round(std::accumulate(y_coords.begin(), y_coords.end(), 0.f) / (double)y_coords.size())};
 
             // Save offset for this tile/ptc combo
-            if (physical_type_offsets.find(tile_type) == physical_type_offsets.end())
+            if (!physical_type_offsets.contains(tile_type))
                 physical_type_offsets[tile_type] = {};
 
             physical_type_offsets[tile_type].insert({node_ptc, new_loc - tile_bb.bottom_left()});

vpr/src/base/vpr_context.h

@@ -44,7 +44,7 @@
 class SetupHoldTimingInfo;
 class PostClusterDelayCalculator;
 
-#endif /* NO_SERVER */
+#endif // NO_SERVER
 
 struct t_rr_node_route_inf;
 
@@ -143,22 +143,10 @@ struct TimingContext : public Context {
 
     t_timing_analysis_profile_info stats;
 
-    /* Represents whether or not VPR should fail if timing constraints aren't met. */
+    /// Represents whether VPR should fail if timing constraints aren't met.
     bool terminate_if_timing_fails = false;
 };
 
-namespace std {
-template<>
-struct hash<std::tuple<int, int, short>> {
-    std::size_t operator()(const std::tuple<int, int, short>& ok) const noexcept {
-        std::size_t seed = std::hash<int>{}(std::get<0>(ok));
-        vtr::hash_combine(seed, std::get<1>(ok));
-        vtr::hash_combine(seed, std::get<2>(ok));
-        return seed;
-    }
-};
-} // namespace std
-
 /**
  * @brief State relating the device
  *
@@ -200,11 +188,9 @@ struct DeviceContext : public Context {
     std::vector<t_physical_tile_type> physical_tile_types;
     std::vector<t_logical_block_type> logical_block_types;
 
-    /*
-     * Keep which layer in multi-die FPGA require inter-cluster programmable routing resources [0..number_of_layers-1]
-     * If a layer doesn't require inter-cluster programmable routing resources,
-     * RRGraph generation will ignore building SBs and CBs for that specific layer.
-     */
+    /// Keep which layer in multi-die FPGA require inter-cluster programmable routing resources [0..number_of_layers-1]
+    /// If a layer doesn't require inter-cluster programmable routing resources,
+    /// RRGraph generation will ignore building SBs and CBs for that specific layer.
     std::vector<bool> inter_cluster_prog_routing_resources;
 
     /**
@@ -373,7 +359,7 @@ struct ClusteringContext : public Context {
 /**
  * @brief State relating to packing multithreading
  *
- * This contain data structures to synchronize multithreading of packing iterative improvement.
+ * This contains data structures to synchronize multithreading of packing iterative improvement.
  */
 struct PackingMultithreadingContext : public Context {
     vtr::vector<ClusterBlockId, bool> clb_in_flight;
@@ -770,7 +756,7 @@ struct ServerContext : public Context {
      */
     std::shared_ptr<PostClusterDelayCalculator> routing_delay_calc;
 };
-#endif /* NO_SERVER */
+#endif // NO_SERVER
 
 /**
  * @brief This object encapsulates VPR's state.
@@ -855,7 +841,7 @@ class VprContext : public Context {
 #ifndef NO_SERVER
     const ServerContext& server() const { return server_; }
     ServerContext& mutable_server() { return server_; }
-#endif /* NO_SERVER */
+#endif // NO_SERVER
 
   private:
     DeviceContext device_;
@@ -873,7 +859,7 @@ class VprContext : public Context {
 
 #ifndef NO_SERVER
     ServerContext server_;
-#endif /* NO_SERVER */
+#endif // NO_SERVER
 
     PackingMultithreadingContext packing_multithreading_;
 };

vpr/src/route/rr_graph_generation/build_scatter_gathers.cpp

@@ -399,8 +399,10 @@ void convert_interposer_cuts_to_sg_patterns(const std::vector<t_layer_def>& inte
 void compute_non_3d_sg_link_geometry(const t_physical_tile_loc& src_loc,
                                      const t_physical_tile_loc& dst_loc,
                                      e_rr_type& chan_type,
-                                     int& xlow, int& xhigh,
-                                     int& ylow, int& yhigh,
+                                     int& xlow,
+                                     int& xhigh,
+                                     int& ylow,
+                                     int& yhigh,
                                      Direction& direction) {
     VTR_ASSERT_SAFE(src_loc.layer_num == dst_loc.layer_num);
 
@@ -431,4 +433,4 @@ void compute_non_3d_sg_link_geometry(const t_physical_tile_loc& src_loc,
     } else {
         VTR_ASSERT_MSG(false, "Source and destination locations cannot be identical");
     }
-}
+}

vpr/src/route/rr_graph_generation/build_scatter_gathers.h

@@ -78,12 +78,14 @@ void convert_interposer_cuts_to_sg_patterns(const std::vector<t_layer_def>& inte
                                             std::vector<t_scatter_gather_pattern>& sg_patterns);
 
 /**
-* @brief Computes the channel type, direction, and coordinate span between two locations
-*        on the same layer. Used by SG link construction routines to determine geometry.
-*/
+ * @brief Computes the channel type, direction, and coordinate span between two locations
+ *        on the same layer. Used by SG link construction routines to determine geometry.
+ */
 void compute_non_3d_sg_link_geometry(const t_physical_tile_loc& src_loc,
                                      const t_physical_tile_loc& dst_loc,
                                      e_rr_type& chan_type,
-                                     int& xlow, int& xhigh,
-                                     int& ylow, int& yhigh,
-                                     Direction& direction);
+                                     int& xlow,
+                                     int& xhigh,
+                                     int& ylow,
+                                     int& yhigh,
+                                     Direction& direction);