Skip to content

Conversation

@AlexandreSinger
Copy link
Contributor

The code for reading a netlist file was very hard to follow and made it challenging to try and improve the pb interface. Went through and cleaned up the code to make it a bit more obvious what it is trying to do.

The code for reading a netlist file was very hard to follow and made it
challenging to try and improve the pb interface. Went through and
cleaned up the code to make it a bit more obvious what it is trying to
do.
@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code labels Nov 1, 2025
Copy link
Contributor

@AmirhosseinPoolad AmirhosseinPoolad left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thanks for the PR Alex. Had some thoughts. About the autos, I didn't tag all of them here so you might want to do a CTRL+F for auto to see all of them. I also didn't tag all the functions that were missing doxygen docs.

if (hash_value->count == 1) {
VTR_ASSERT(*ncount == hash_value->index);
(*ncount)++;
processPb(child, index, new_child_pb, pb_route, num_primitives, loc_data);
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I think we should refactor these functions to net be recursive. If we want to clean up the packer we really need to get rid of the recursions in these massive functions.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This function is used for parsing XML. Unfortunately removing this recursion will be very challenging to do and may actually take away from the readability of this function. I think it will be best to leave this update behind for now. In the future when the t_pb type is cleaned up a bit more, I hope to absorb this method in a cleaner way.

pin_node = alloc_and_load_port_pin_ptrs_from_string(
int* num_ptrs = nullptr;
int num_sets = 0;
t_pb_graph_pin*** pin_node = alloc_and_load_port_pin_ptrs_from_string(
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Is this a 3D array or a 2D array of pointers? We should convert this to std::vector.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This is a 2D array of pins. I also do not like this, but I think this will be better cleaned up in a future PR. This is drilled into how pb types are stored in VTR right now. I would prefer to leave it alone in this PR.

const t_pb_type* child_pb_type = &(pb_type->modes[pb->mode].pb_type_children[i]);
for (int j = 0; j < child_pb_type->num_pb; j++) {
if (pb->child_pbs[i][j].name != nullptr) {
const_gen_count += mark_constant_generators_rec(&(pb->child_pbs[i][j]), pb_route, verbosity);
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Same as above. It's incredibly hard to understand how exactly these functions work with the recursion.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I also agree that recursion can make code a bit challenging to work with; however, the way that the pb_types are currently designed, recursion is the cleanest way of iterating over them. I hope to remove this limitation in a future PR.

@AlexandreSinger
Copy link
Contributor Author

@AmirhosseinPoolad I have resolve your comments, and left a note for any comments I do not think should change. Please let me know if you have any further comments.

@AlexandreSinger
Copy link
Contributor Author

Thanks for the feedback @soheilshahrouz , resolved. Please let me know if you have any further comments.

@AlexandreSinger AlexandreSinger merged commit 07addcc into verilog-to-routing:master Nov 3, 2025
30 checks passed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

lang-cpp C/C++ code VPR VPR FPGA Placement & Routing Tool

Projects

None yet

Development

Successfully merging this pull request may close these issues.

3 participants