Merge pull request #3239 from verilog-to-routing/fixing_primitives_for_slang

Switching to Non-Blocking Assigns in Single/Dual Port Ram Primitives

Author: vaughnbetz

parmys/third_party/vtr_flow/primitives.v

@@ -266,9 +266,9 @@ module single_port_ram #(
 
     always@(posedge clk) begin
         if(we) begin
-            Mem[addr] = data;
+            Mem[addr] <= data;
         end
-    	out = Mem[addr]; //New data read-during write behaviour (blocking assignments)
+    	out <= Mem[addr]; //Old data read-first behaviour (non-blocking assignments)
     end
 
 endmodule // single_port_RAM
@@ -314,16 +314,16 @@ module dual_port_ram #(
 
     always@(posedge clk) begin //Port 1
         if(we1) begin
-            Mem[addr1] = data1;
+            Mem[addr1] <= data1;
         end
-        out1 = Mem[addr1]; //New data read-during write behaviour (blocking assignments)
+        out1 <= Mem[addr1]; //Old data read-first behaviour (non-blocking assignments)
     end
 
     always@(posedge clk) begin //Port 2
         if(we2) begin
-            Mem[addr2] = data2;
+            Mem[addr2] <= data2;
         end
-        out2 = Mem[addr2]; //New data read-during write behaviour (blocking assignments)
+        out2 <= Mem[addr2]; //Old data read-first behaviour (non-blocking assignments)
     end
 
 endmodule // dual_port_ram

vtr_flow/primitives.v

@@ -266,9 +266,9 @@ module single_port_ram #(
 
     always@(posedge clk) begin
         if(we) begin
-            Mem[addr] = data;
+            Mem[addr] <= data;
         end
-    	out = Mem[addr]; //New data read-during write behaviour (blocking assignments)
+    	out <= Mem[addr]; //Old data read-first behaviour (non-blocking assignments)
     end
 
 endmodule // single_port_RAM
@@ -314,16 +314,16 @@ module dual_port_ram #(
 
     always@(posedge clk) begin //Port 1
         if(we1) begin
-            Mem[addr1] = data1;
+            Mem[addr1] <= data1;
         end
-        out1 = Mem[addr1]; //New data read-during write behaviour (blocking assignments)
+        out1 <= Mem[addr1]; //Old data read-first behaviour (non-blocking assignments)
     end
 
     always@(posedge clk) begin //Port 2
         if(we2) begin
-            Mem[addr2] = data2;
+            Mem[addr2] <= data2;
         end
-        out2 = Mem[addr2]; //New data read-during write behaviour (blocking assignments)
+        out2 <= Mem[addr2]; //Old data read-first behaviour (non-blocking assignments)
     end
 
 endmodule // dual_port_ram