Modifying comments to reflect new changes to single and dual port ram primitives

Author: loglav03

parmys/third_party/vtr_flow/primitives.v

@@ -268,7 +268,7 @@ module single_port_ram #(
         if(we) begin
             Mem[addr] <= data;
         end
-    	out <= Mem[addr]; //New data read-during write behaviour (blocking assignments)
+    	out <= Mem[addr]; //Old data read-first behaviour (non-blocking assignments)
     end
 
 endmodule // single_port_RAM
@@ -316,14 +316,14 @@ module dual_port_ram #(
         if(we1) begin
             Mem[addr1] <= data1;
         end
-        out1 <= Mem[addr1]; //New data read-during write behaviour (blocking assignments)
+        out1 <= Mem[addr1]; //Old data read-first behaviour (non-blocking assignments)
     end
 
     always@(posedge clk) begin //Port 2
         if(we2) begin
             Mem[addr2] <= data2;
         end
-        out2 <= Mem[addr2]; //New data read-during write behaviour (blocking assignments)
+        out2 <= Mem[addr2]; //Old data read-first behaviour (non-blocking assignments)
     end
 
 endmodule // dual_port_ram

vtr_flow/primitives.v

@@ -268,7 +268,7 @@ module single_port_ram #(
         if(we) begin
             Mem[addr] <= data;
         end
-    	out <= Mem[addr]; //New data read-during write behaviour (blocking assignments)
+    	out <= Mem[addr]; //Old data read-first behaviour (non-blocking assignments)
     end
 
 endmodule // single_port_RAM
@@ -314,16 +314,16 @@ module dual_port_ram #(
 
     always@(posedge clk) begin //Port 1
         if(we1) begin
-            Mem[addr1] = data1;
+            Mem[addr1] <= data1;
         end
-        out1 = Mem[addr1]; //New data read-during write behaviour (blocking assignments)
+        out1 <= Mem[addr1]; //Old data read-first behaviour (non-blocking assignments)
     end
 
     always@(posedge clk) begin //Port 2
         if(we2) begin
             Mem[addr2] <= data2;
         end
-        out2 <= Mem[addr2]; //New data read-during write behaviour (blocking assignments)
+        out2 <= Mem[addr2]; //Old data read-first behaviour (non-blocking assignments)
     end
 
 endmodule // dual_port_ram