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rtl-verification

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ramiomer94 / VLSI-design-projects

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This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

verilog semiconductor-physics genus custom-layout virtuoso digital-logic-design static-timing-analysis vlsi-design asic-design rtl-design innovus standard-cells eda-tools rtl-verification cmos-design rtl-to-gdsii cadence-tools
  • Updated Jul 12, 2025
  • Verilog

Hithaishisr / verification-of-apb-based-uart-master-core

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UVM-based functional verification of an APB-based UART Master Core RTL. Includes multi-agent environment, assertions, coverage collection, and multiple test scenarios (full/half duplex, parity, framing, timeout errors) achieving 100% functional coverage and protocol compliance.

fpga eda uart systemverilog vlsi uvm testbench digital-design serial-communication apb functional-verification hardware-verification rtl-design rtl-verification uvm-environment
  • Updated Nov 1, 2025
  • SystemVerilog

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