32-bit Superscalar RISC-V CPU

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

CPU Benchmarks Set

CoreMark 1.0 ported to WebAssembly

LEVEL: Open-source RV32IMC RISC-V processor core with pipelined microarchitecture, cache support, SoC peripherals and verification framework.

This repository utilizes CoreMark as the benchmarking core for evaluating microcontrollers.

STM32CubeMX Pack for Easy Integration of CoreMark

A 6-Stage RISC-V RV32IM Core on FPGA (263.7 CoreMark, 91.0 DMIPS@100MHz)

Minimalist Kernel Providing Test Environment

Forth language port of CoreMark benchmark (https://www.eembc.org/coremark)

Design guidelines and performance analysis for 10 RISC-V 5- to 8-stage pipeline variants based on basic_RV32S and IMA_make_RV64, covering ISA extension scaling, pipeline-depth sweep, and 100 MHz(125) timing closure on Artix-7 FPGA.

Autonomous RISC-V CPU replication of 'Design Conductor' (arxiv:2603.08716) — 1.525 GHz, 2,358 µm² cell area, CoreMark 9,541, ASAP7 SLVT, open-source EDA only. Personal side project.

This work presents the design and implementation of high performance and low power 32-bit RISC-V processor 4-stage pipelined for non-load and 5-stage for load operations, also extending its capabilities as system on chip (SoC) design. RV32I with M extension designed for FPGA and ASIC

ArduinoCoreMark is a CPU performance benchmark for Arduino platform based on EEMBC CoreMark.

Architecture and Performance Evaluation of EEMBC::CoreMark benchmark on BOOM CPUs (Small & Large).

Raspberry Pi Pico Coremark

Cycle-approximate out-of-order RISC-V CPU simulator with TAGE branch prediction, store-to-load forwarding, and a genetic algorithm for design space exploration using real CoreMark execution.

Coremark for iMXRT1170 Dual Core

CoreMark's primary goals are simplicity and providing a method for testing only a processor's core features.

A stable version of nexus-am (created by jyy).