RISC-V XV6/Linux SoC, marchID: 0x2b, 0x34
ElemRV - End-to-end Open-Source RISC-V Microcontroller
A parameterizable Weight-Stationary 2D Systolic Array implemented in Verilog for hardware-accelerated matrix multiplication
Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF
SVDB Gateway : DPI-C library that links SystemVerilog simulations with external SQLite databases for configuration, logging, and verification.
BLogic MCU - RISC-V (CV32E40P, RV32IMC) microcontroller SoC with a custom AXI4 interconnect and a TinyConv keyword-spotting AI accelerator (21× vs software). sky130 GDSII signed off at 27 MHz, runs on a Genesys 2 FPGA at 50 MHz, JTAG debug. TEKNOFEST 2026 Chip Design Competition - OSTİM Technical University
An open source SoC project for the VLSI 2 class at ETHZ. Selected as one of the best design and taped out in IHP 130nm technology
An OpenSource FreeCAD plugin for the BMBF project DI-Passionate to enable chip-packaging
Chipro First Agentic EDA Design System
this verilog repo is my commitment to cover the all basic stuffs and syntax of the verilog in one week +1-2 days more if required and will upload the projects made with the verilog in this repo too
A BJT NPN transistor, who's layout resembles it's electronics symbol.
VSDIAT Documentation- Openlane/Sky130- MIT
AI-native digital IC orchestration platform that transforms natural language specifications into verified RTL and manufacturable GDSII through observable, browser-native workflows.
setup ur oown deployment , dont make any changes in mine. samjhe ke nhi
The Soil Moisture Irrigation Controller is a finite state machine (FSM) that automatically controls an irrigation pump based on soil moisture levels.
A programmable pin-bit-banging core that speaks UART, SPI, and I²C from firmware. Jane Street 2027 ASIC competition entry, targeting Tiny Tapeout on IHP CMOS5L.
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