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34 changes: 19 additions & 15 deletions lib/IRGen/GenCall.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -870,26 +870,30 @@ void SignatureExpansion::expandCoroutineResult(bool forContinuation) {
}

// Find the maximal sequence of the component types that we can
// convince the ABI to pass directly.
// convince the ABI to pass directly if the target supports
// directly returning at least two pointers.
// When counting components, ignore the continuation pointer.
unsigned numDirectComponents = components.size() - 1;
SmallVector<llvm::Type*, 8> overflowTypes;
while (clang::CodeGen::swiftcall::
shouldPassIndirectly(IGM.ClangCodeGen->CGM(), components,
/*asReturnValue*/ true)) {
// If we added a pointer to the end of components, remove it.
if (!overflowTypes.empty()) components.pop_back();
unsigned numDirectComponents = components.size() - 1;
if (IGM.TargetInfo.SupportsDirectReturningAtLeastTwoPointers) {
while (clang::CodeGen::swiftcall::shouldPassIndirectly(
IGM.ClangCodeGen->CGM(), components,
/*asReturnValue*/ true)) {
// If we added a pointer to the end of components, remove it.
if (!overflowTypes.empty())
components.pop_back();

// Remove the last component and add it as an overflow type.
overflowTypes.push_back(components.pop_back_val());
--numDirectComponents;
// Remove the last component and add it as an overflow type.
overflowTypes.push_back(components.pop_back_val());
--numDirectComponents;

// Add a pointer to the end of components.
components.push_back(IGM.Int8PtrTy);
}
// Add a pointer to the end of components.
components.push_back(IGM.Int8PtrTy);
}

// We'd better have been able to pass at least two pointers.
assert(components.size() >= 2 || overflowTypes.empty());
// We'd better have been able to pass at least two pointers.
assert(components.size() >= 2 || overflowTypes.empty());
}
CoroInfo.NumDirectYieldComponents = numDirectComponents;

// Replace the pointer type we added to components with the real
Expand Down
150 changes: 104 additions & 46 deletions lib/IRGen/LoadableByAddress.cpp

Large diffs are not rendered by default.

12 changes: 10 additions & 2 deletions lib/IRGen/SwiftTargetInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -17,12 +17,13 @@

#include "SwiftTargetInfo.h"
#include "IRGenModule.h"
#include "llvm/TargetParser/Triple.h"
#include "llvm/IR/DataLayout.h"
#include "swift/ABI/System.h"
#include "swift/AST/ASTContext.h"
#include "swift/AST/IRGenOptions.h"
#include "swift/Basic/Platform.h"
#include "clang/CodeGen/SwiftCallingConv.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/TargetParser/Triple.h"

using namespace swift;
using namespace irgen;
Expand Down Expand Up @@ -194,6 +195,13 @@ static void configureWasm32(IRGenModule &IGM, const llvm::Triple &triple,
SwiftTargetInfo &target) {
target.LeastValidPointerValue =
SWIFT_ABI_WASM32_LEAST_VALID_POINTER;

// Determine whether the target ABI supports returning two pointers directly.
llvm::Type *ptrTy = llvm::PointerType::getUnqual(IGM.getLLVMContext());
target.SupportsDirectReturningAtLeastTwoPointers =
!clang::CodeGen::swiftcall::shouldPassIndirectly(IGM.getClangCGM(),
{ptrTy, ptrTy},
/*asReturnValue*/ true);
}

/// Configure a default target.
Expand Down
3 changes: 3 additions & 0 deletions lib/IRGen/SwiftTargetInfo.h
Original file line number Diff line number Diff line change
Expand Up @@ -118,6 +118,9 @@ class SwiftTargetInfo {
bool HasSwiftSwiftDirectRuntimeLibrary = false;

bool UsableSwiftAsyncContextAddrIntrinsic = false;

/// True if the target supports directly returning at least two pointers.
bool SupportsDirectReturningAtLeastTwoPointers = true;
};

}
Expand Down
1 change: 1 addition & 0 deletions test/IRGen/async/builtin_executor.sil
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@
// REQUIRES: concurrency
// rdar://106849189 move-only types should be supported in freestanding mode
// UNSUPPORTED: freestanding
// UNSUPPORTED: CPU=wasm32

sil_stage canonical

Expand Down
2 changes: 1 addition & 1 deletion test/IRGen/async/partial_apply.sil
Original file line number Diff line number Diff line change
Expand Up @@ -606,7 +606,7 @@ entry(%0 : $EmptyType, %1: $*SomeType, %3: $FixedType):
return %40 : $()
}

// CHECK-LABEL: define{{( dllexport)?}}{{( protected)?}} swift{{(tail)?}}cc { ptr, ptr } @create_pa_f2(
// CHECK-LABEL: define{{( dllexport)?}}{{( protected)?}} swift{{(tail)?}}cc {{{ ptr, ptr }|void}} @create_pa_f2(
sil @create_pa_f2 : $@convention(thin) (@callee_guaranteed @async @convention(thick) (Int64, Int32) -> Int64, Int32) -> @owned @async @callee_guaranteed (Int64) -> Int64 {
bb0(%thick : $@callee_guaranteed @async @convention(thick) (Int64, Int32) -> Int64 , %captured : $Int32):
%pa_f = partial_apply [callee_guaranteed] %thick(%captured) : $@callee_guaranteed @async @convention(thick) (Int64, Int32) -> Int64
Expand Down
1 change: 1 addition & 0 deletions test/IRGen/big_types_corner_cases.swift
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@
// RUN: %target-swift-frontend -disable-type-layout %s -emit-ir | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-ptrsize
// REQUIRES: optimized_stdlib
// UNSUPPORTED: CPU=powerpc64le
// UNSUPPORTED: CPU=wasm32

public struct BigStruct {
var i0 : Int32 = 0
Expand Down
1 change: 1 addition & 0 deletions test/IRGen/boxed_existential.sil
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
// RUN: %target-swift-frontend %s -emit-ir | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-ptrsize --check-prefix=CHECK-%target-runtime
// UNSUPPORTED: CPU=wasm32

import Swift

Expand Down
28 changes: 14 additions & 14 deletions test/IRGen/builtin_freeze.swift
Original file line number Diff line number Diff line change
Expand Up @@ -27,30 +27,30 @@ func yum() -> Int32 {
}
// CHECK: }

func fptosi(_ x: SIMD2<Float>) -> SIMD2<Int32> {
let maybePoison = Builtin.fptosi_Vec2xFPIEEE32_Vec2xInt32(x._storage._value)
var result = SIMD2<Int32>()
func fptosi(_ x: SIMD4<Float>) -> SIMD4<Int32> {
let maybePoison = Builtin.fptosi_Vec4xFPIEEE32_Vec4xInt32(x._storage._value)
var result = SIMD4<Int32>()
result._storage._value = maybePoison
return result
// CHECK: fptosi <2 x float> %{{.+}} to <2 x i32>
// CHECK: fptosi <4 x float> %{{.+}} to <4 x i32>
}

func fptosiWithFreeze(_ x: SIMD2<Float>) -> SIMD2<Int32> {
let maybePoison = Builtin.fptosi_Vec2xFPIEEE32_Vec2xInt32(x._storage._value)
let frozen = Builtin.freeze_Vec2xInt32(maybePoison)
var result = SIMD2<Int32>()
func fptosiWithFreeze(_ x: SIMD4<Float>) -> SIMD4<Int32> {
let maybePoison = Builtin.fptosi_Vec4xFPIEEE32_Vec4xInt32(x._storage._value)
let frozen = Builtin.freeze_Vec4xInt32(maybePoison)
var result = SIMD4<Int32>()
result._storage._value = frozen
return result
// CHECK: fptosi <2 x float> %{{.+}} to <2 x i32>
// CHECK-NEXT: freeze <2 x i32> %{{.+}}
// CHECK: fptosi <4 x float> %{{.+}} to <4 x i32>
// CHECK-NEXT: freeze <4 x i32> %{{.+}}
}

func doubleYuck(_ x: SIMD2<Float>) -> SIMD2<Int32> {
fptosi(SIMD2<Float>(repeating: 0x1.0p32))
func doubleYuck(_ x: SIMD4<Float>) -> SIMD4<Int32> {
fptosi(SIMD4<Float>(repeating: 0x1.0p32))
// CHECK: poison
}

func DoubleYum(_ x: SIMD2<Float>) -> SIMD2<Int32> {
fptosiWithFreeze(SIMD2<Float>(repeating: 0x1.0p32))
func DoubleYum(_ x: SIMD4<Float>) -> SIMD4<Int32> {
fptosiWithFreeze(SIMD4<Float>(repeating: 0x1.0p32))
// CHECK-NOT: poison
}
1 change: 1 addition & 0 deletions test/IRGen/builtin_vector_fixed_array.sil
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
// RUN: %target-swift-frontend -emit-irgen -disable-availability-checking -enable-experimental-feature BuiltinModule %s | %FileCheck %s

// REQUIRES: swift_feature_BuiltinModule
// UNSUPPORTED: CPU=wasm32

import Builtin
import Swift
Expand Down
1 change: 1 addition & 0 deletions test/IRGen/enum_dynamic_multi_payload.sil
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
// RUN: %target-swift-frontend -disable-type-layout %s -gnone -emit-ir -I %S/Inputs | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-ptrsize -DINT=i%target-ptrsize --check-prefix=CHECK-%target-cpu
// UNSUPPORTED: CPU=wasm32

import Builtin

Expand Down
1 change: 1 addition & 0 deletions test/IRGen/enum_resilience.swift
Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@
// RUN: %target-swift-frontend -emit-module -enable-library-evolution -emit-module-path=%t/resilient_enum.swiftmodule -module-name=resilient_enum -I %t %S/../Inputs/resilient_enum.swift
// RUN: %target-swift-frontend -disable-type-layout -module-name enum_resilience -I %t -emit-ir -enable-library-evolution %s | %FileCheck %t/enum_resilience.swift -DINT=i%target-ptrsize --check-prefix=CHECK --check-prefix=CHECK-%target-ptrsize --check-prefix=CHECK-%target-cpu
// RUN: %target-swift-frontend -module-name enum_resilience -I %t -emit-ir -enable-library-evolution -O %s
// UNSUPPORTED: CPU=wasm32

import resilient_enum
import resilient_struct
Expand Down
1 change: 1 addition & 0 deletions test/IRGen/errors.sil
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
// XFAIL: CPU=powerpc64le
// XFAIL: CPU=s390x
// RUN: %target-swift-frontend -primary-file %s -emit-ir | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-runtime --check-prefix=CHECK-%target-cpu --check-prefix=CHECK-%target-ptrsize
// UNSUPPORTED: CPU=wasm32

sil_stage canonical

Expand Down
1 change: 1 addition & 0 deletions test/IRGen/isolated_any.sil
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
// RUN: %target-swift-frontend -emit-ir %s | %IRGenFileCheck %s

// REQUIRES: concurrency
// UNSUPPORTED: CPU=wasm32

import Swift
import _Concurrency
Expand Down
1 change: 1 addition & 0 deletions test/IRGen/meta_meta_type.swift
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,7 @@
// RUN: %target-run %t/a.out | %FileCheck %s
// RUN: %target-swift-frontend -primary-file %s -emit-ir | %FileCheck -check-prefix=CHECKIR %s
// REQUIRES: executable_test
// UNSUPPORTED: CPU=wasm32

protocol Proto {
}
Expand Down
4 changes: 2 additions & 2 deletions test/IRGen/objc_simd.sil
Original file line number Diff line number Diff line change
Expand Up @@ -68,7 +68,7 @@ entry(%x : $float3):
// powerpc64-LABEL: define{{( dllexport)?}}{{( protected)?}} void @simd_native_args(ptr noalias sret({{.*}}) captures(none) %0, ptr noalias captures(none) dereferenceable({{.*}}) %1)
// powerpc64le-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc { float, float, float, float } @simd_native_args(float %0, float %1, float %2, float %3)
// s390x-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc { float, float, float, float } @simd_native_args(float %0, float %1, float %2, float %3)
// wasm32-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc { float, float, float, float } @simd_native_args(float %0, float %1, float %2, float %3)
// wasm32-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc void @simd_native_args(ptr noalias sret(%T4simd6float4V) captures(none) %0, float %1, float %2, float %3, float %4)
sil @simd_native_args : $@convention(thin) (float4) -> float4 {
entry(%x : $float4):
%f = function_ref @simd_c_args : $@convention(c) (float4) -> float4
Expand All @@ -87,7 +87,7 @@ entry(%x : $float4):
// powerpc64-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc { float, float, float } @simd_native_args_float3(float %0, float %1, float %2)
// powerpc64le-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc { float, float, float } @simd_native_args_float3(float %0, float %1, float %2)
// s390x-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc { float, float, float } @simd_native_args_float3(float %0, float %1, float %2)
// wasm32-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc { float, float, float } @simd_native_args_float3(float %0, float %1, float %2)
// wasm32-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc void @simd_native_args_float3(ptr noalias sret(%T4simd6float3V) captures(none) %0, float %1, float %2, float %3)
sil @simd_native_args_float3 : $@convention(thin) (float3) -> float3 {
entry(%x : $float3):
%f = function_ref @simd_c_args_float3 : $@convention(c) (float3) -> float3
Expand Down
5 changes: 2 additions & 3 deletions test/IRGen/package-cmo-serialize-witness-thunk.swift
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,6 @@
// RUN: %FileCheck %s --check-prefix=CHECK-IR < %t/Lib-ir.ll
// RUN: %FileCheck %s --check-prefix=CHECK-TBD < %t/Lib-tbd.tbd


/// TEST that a public (or package) protocol witness thunk gets a shared linkage if Package CMO is enabled.
/// It also gets [serialized] in emit-silgen.
///
Expand All @@ -33,8 +32,8 @@
// CHECK-NO-PCMO-SIL-DAG: sil private [transparent] [thunk] @$s3Lib3PubVAA5ProtoA2aDP3fooSSvgTW : $@convention(witness_method: Proto) (@in_guaranteed Pub) -> @owned String {
// CHECK-SIL-DAG: sil shared [transparent] [thunk] @$s3Lib3PubVAA5ProtoA2aDP3fooSSvgTW : $@convention(witness_method: Proto) (@in_guaranteed Pub) -> @owned String {

// CHECK-NO-PCMO-IR-DAG: define internal swiftcc { {{i64, ptr|i32, i32, i32}} } @"$s3Lib3PubVAA5ProtoA2aDP3fooSSvgTW"
// CHECK-IR-DAG: define linkonce_odr hidden swiftcc { {{i64, ptr|i32, i32, i32}} } @"$s3Lib3PubVAA5ProtoA2aDP3fooSSvgTW"
// CHECK-NO-PCMO-IR-DAG: define internal swiftcc {{{ i64, ptr }|{ i32, i32, i32 }|void}} @"$s3Lib3PubVAA5ProtoA2aDP3fooSSvgTW"
// CHECK-IR-DAG: define linkonce_odr hidden swiftcc {{{ i64, ptr }|{ i32, i32, i32 }|void}} @"$s3Lib3PubVAA5ProtoA2aDP3fooSSvgTW"

// protocol witness for Proto.bar(_:) in conformance Pub

Expand Down
2 changes: 1 addition & 1 deletion test/IRGen/package_bypass_resilience_class.swift
Original file line number Diff line number Diff line change
Expand Up @@ -130,7 +130,7 @@ class UFIKlass {
var varNonUfi: String?

// variable initialization expression of Core.UFIKlass.varUfi
// CHECK-OPT-DAG: define {{(dllexport |protected )?}}swiftcc {{.*}} @"$s4Core8UFIKlassC6varUfiSSSgvpfi"()
// CHECK-OPT-DAG: define {{(dllexport |protected )?}}swiftcc {{.*}} @"$s4Core8UFIKlassC6varUfiSSSgvpfi"

// key path getter for Core.UFIKlass.varUfi
// CHECK-COMMON-DAG: define linkonce_odr hidden swiftcc void @"$s4Core8UFIKlassC6varUfiSSSgvpACTK"
Expand Down
1 change: 1 addition & 0 deletions test/IRGen/partial_apply_coro.sil
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@
// RUN: %target-swift-frontend -Xllvm -sil-disable-pass=OnoneSimplification -I %t -emit-ir -disable-emit-type-malloc-for-coro-frame %s -o - | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-ptrsize --check-prefix=CHECK-%target-cpu

// REQUIRES: concurrency
// UNSUPPORTED: CPU=wasm32

import Builtin
import Swift
Expand Down
1 change: 1 addition & 0 deletions test/IRGen/simple_partial_apply.sil
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
// RUN: %target-swift-frontend -emit-ir %s | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-cpu
// UNSUPPORTED: CPU=wasm32

sil_stage canonical

Expand Down
1 change: 1 addition & 0 deletions test/IRGen/struct_resilience.swift
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@
// RUN: %target-swift-frontend -emit-module -enable-library-evolution -emit-module-path=%t/resilient_enum.swiftmodule -module-name=resilient_enum -I %t %S/../Inputs/resilient_enum.swift
// RUN: %target-swift-frontend -module-name struct_resilience -Xllvm -sil-disable-pass=MandatoryARCOpts -I %t -emit-ir -enable-library-evolution %s | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-cpu
// RUN: %target-swift-frontend -module-name struct_resilience -I %t -emit-ir -enable-library-evolution -O %s
// UNSUPPORTED: CPU=wasm32

import resilient_struct
import resilient_enum
Expand Down
1 change: 1 addition & 0 deletions test/IRGen/subclass_existentials.sil
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
// RUN: %target-swift-frontend -primary-file %s -emit-ir | %FileCheck %s --check-prefix=CHECK-%target-runtime --check-prefix=CHECK -DINT=i%target-ptrsize
// UNSUPPORTED: CPU=wasm32

sil_stage canonical

Expand Down
1 change: 1 addition & 0 deletions test/IRGen/variadic_generic_captures.swift
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
// RUN: %target-swift-frontend -emit-ir %s | %FileCheck %s -DINT=i%target-ptrsize
// UNSUPPORTED: CPU=wasm32

public func takesNoEscape(_: () -> ()) {}

Expand Down
1 change: 1 addition & 0 deletions test/IRGen/yield_once_biggish.sil
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@
// we should turn this into a REQUIRES instead.
// UNSUPPORTED: CPU=i386
// UNSUPPORTED: CPU=arm64_32
// UNSUPPORTED: CPU=wasm32

import Builtin
import Swift
Expand Down
1 change: 1 addition & 0 deletions test/IRGen/yield_result.sil
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
// RUN: %target-swift-frontend -emit-irgen -disable-emit-type-malloc-for-coro-frame %s | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-cpu --check-prefix=CHECK-%target-ptrsize -DINT=i%target-ptrsize
// UNSUPPORTED: CPU=wasm32

import Builtin

Expand Down
4 changes: 2 additions & 2 deletions test/embedded/linkage/export_interface.swift
Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ private func throughPrivate() -> [Int] {
// LIBRARY-IR-NOT: unnecessary
public func unnecessary() -> Int { 5 }

// LIBRARY-IR: define linkonce_odr hidden swiftcc { ptr, ptr } @"$es27_allocateUninitializedArrayySayxG_BptBwlFSi_Tg5"
// LIBRARY-IR: define linkonce_odr hidden swiftcc {{{ ptr, ptr }|void}} @"$es27_allocateUninitializedArrayySayxG_BptBwlFSi_Tg5"

// LIBRARY-SIL: sil @$e7Library5helloSaySiGyF
// LIBRARY-SIL: sil @$e7Library8getArraySaySiGyF : $@convention(thin) () -> @owned Array<Int> {
Expand Down Expand Up @@ -77,5 +77,5 @@ struct Main {
}
}

// APPLICATION-IR: define linkonce_odr hidden swiftcc { ptr, ptr } @"$es27_allocateUninitializedArrayySayxG_BptBwlFSi_Tg5"
// APPLICATION-IR: define linkonce_odr hidden swiftcc {{{ ptr, ptr }|void}} @"$es27_allocateUninitializedArrayySayxG_BptBwlFSi_Tg5"

4 changes: 2 additions & 2 deletions test/embedded/linkage/leaf_application.swift
Original file line number Diff line number Diff line change
Expand Up @@ -77,7 +77,7 @@ extension PointClass: Reflectable {
}
}

// LIBRARY-IR: define {{.*}} @"$e7Library18createsExistentialAA11Reflectable_pyF"()
// LIBRARY-IR: define {{.*}} @"$e7Library18createsExistentialAA11Reflectable_pyF"
@export(interface)
public func createsExistential() -> any Reflectable {
return PointClass(x: 5, y: 5)
Expand Down Expand Up @@ -112,7 +112,7 @@ public func testMe() {

// APPLICATION-IR: define {{(protected |dllexport )?}}i32 @Application_main

// APPLICATION-IR: define linkonce_odr hidden swiftcc { ptr, ptr } @"$es27_allocateUninitializedArrayySayxG_BptBwlFSi_Tg5"
// APPLICATION-IR: define linkonce_odr hidden swiftcc {{{ ptr, ptr }|void}} @"$es27_allocateUninitializedArrayySayxG_BptBwlFSi_Tg5"

@main
struct Main {
Expand Down
2 changes: 1 addition & 1 deletion test/embedded/linkage/leaf_library.swift
Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@ private func throughPrivate() -> [Int] {
[5, 6, 7]
}

// LIBRARY-IR: define linkonce_odr hidden swiftcc { ptr, ptr } @"$es27_allocateUninitializedArrayySayxG_BptBwlFSi_Tg5"
// LIBRARY-IR: define linkonce_odr hidden swiftcc {{{ ptr, ptr }|void}} @"$es27_allocateUninitializedArrayySayxG_BptBwlFSi_Tg5"

// LIBRARY-IR: define {{(protected |dllexport )?}}swiftcc i64 @"$e7Library11unnecessarys5Int64VyF"()
public func unnecessary() -> Int64 { 5 }
Expand Down
4 changes: 2 additions & 2 deletions test/stdlib/SIMDFloatInitializers.swift.gyb
Original file line number Diff line number Diff line change
Expand Up @@ -37,9 +37,9 @@ func repeating${n}x${bits}(_ scalar: ${scalar}) -> SIMD${n}<${scalar}> {
% if bits == 16:
#endif
% end
// CHECK${arch}: repeating${n}x${bits}{{.*}} {
// CHECK${arch}: define {{.*}} @"{{.*}}repeating${n}x${bits}{{.*}}"({{(ptr noalias sret\(.+\) captures\(none\) %0, )?}}{{(.+)}} [[ARG:%[0-9]+]])
// CHECK${arch}: entry:
// CHECK${arch}: [[TMP:%[0-9]+]] = insertelement <${n} x ${llvm}> {{.*}} ${llvm} %0, i32 0
// CHECK${arch}: [[TMP:%[0-9]+]] = insertelement <${n} x ${llvm}> {{.*}} ${llvm} [[ARG]], i32 0
// CHECK${arch}-NEXT: [[REP:%[0-9]+]] = shufflevector <${n} x ${llvm}> [[TMP]], <${n} x ${llvm}> {{.*}}, <${n} x i32> zeroinitializer

% end
Expand Down
4 changes: 2 additions & 2 deletions test/stdlib/SIMDSignedInitializers.swift.gyb
Original file line number Diff line number Diff line change
Expand Up @@ -23,9 +23,9 @@ import Swift
func repeating${n}_int${bits}(_ scalar: Int${bits}) -> SIMD${n}<Int${bits}> {
SIMD${n}(repeating: scalar)
}
// CHECK: repeating${n}_int${bits}{{.*}} {
// CHECK: define {{.*}} @"{{.*}}repeating${n}_int${bits}{{.*}}"({{(ptr noalias sret\(.+\) captures\(none\) %0, )?}}{{(.+)}} [[ARG:%[0-9]+]])
// CHECK: entry:
// CHECK: [[TMP:%[0-9]+]] = insertelement <${n} x i${bits}> {{.*}}, i${bits} %0, i32 0
// CHECK: [[TMP:%[0-9]+]] = insertelement <${n} x i${bits}> {{.*}}, i${bits} [[ARG]], i32 0
// CHECK-NEXT: [[REP:%[0-9]+]] = shufflevector <${n} x i${bits}> [[TMP]], <${n} x i${bits}> {{.*}}, <${n} x i32> zeroinitializer

% end
Expand Down