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Merge branch 'main' into add_tdp_ram2
2 parents 24cd4de + 7086a94 commit b4c27b8

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11 files changed

+140
-40
lines changed

11 files changed

+140
-40
lines changed

lambdalib/stdlib/la_csa42/rtl/la_csa42.v

Lines changed: 11 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -4,9 +4,11 @@
44
//# License: MIT (see LICENSE file in Lambda repository) #
55
//#############################################################################
66

7-
module la_csa42 #(
7+
module la_csa42
8+
#(
89
parameter PROP = "DEFAULT"
9-
) (
10+
)
11+
(
1012
input a,
1113
input b,
1214
input c,
@@ -15,11 +17,13 @@ module la_csa42 #(
1517
output sum,
1618
output carry,
1719
output cout
18-
);
20+
);
1921

20-
assign cout = (a & b) | (b & c) | (a & c);
21-
assign sumint = a ^ b ^ c;
22-
assign sum = cin ^ d ^ sumint;
23-
assign carry = (cin & d) | (cin & sumint) | (d & sumint);
22+
wire sumint;
23+
24+
assign cout = (a & b) | (b & c) | (a & c);
25+
assign sumint = a ^ b ^ c;
26+
assign sum = cin ^ d ^ sumint;
27+
assign carry = (cin & d) | (cin & sumint) | (d & sumint);
2428

2529
endmodule

lambdalib/veclib/__init__.py

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,11 @@
11
from siliconcompiler import Design
22

33
from .la_vbuf.la_vbuf import Vbuf
4+
from .la_vdffnq.la_vdffnq import Vdffnq
5+
from .la_vdffq.la_vdffq import Vdffq
46
from .la_vinv.la_vinv import Vinv
7+
from .la_vlatnq.la_vlatnq import Vlatnq
8+
from .la_vlatq.la_vlatq import Vlatq
59
from .la_vmux.la_vmux import Vmux
610
from .la_vmux2b.la_vmux2b import Vmux2b
711
from .la_vmux2.la_vmux2 import Vmux2
@@ -11,10 +15,13 @@
1115
from .la_vmux6.la_vmux6 import Vmux6
1216
from .la_vmux7.la_vmux7 import Vmux7
1317
from .la_vmux8.la_vmux8 import Vmux8
14-
from .la_vpriority.la_vpriority import Vpriority
1518

1619
__all__ = ['Vbuf',
20+
'Vdffnq',
21+
'Vdffq',
1722
'Vinv',
23+
'Vlatnq',
24+
'Vlatq',
1825
'Vmux',
1926
'Vmux2',
2027
'Vmux2b',
@@ -24,7 +31,6 @@
2431
'Vmux6',
2532
'Vmux7',
2633
'Vmux8',
27-
'Vpriority'
2834
]
2935

3036

@@ -34,7 +40,11 @@ def __init__(self):
3440

3541
with self.active_fileset("rtl"):
3642
self.add_depfileset(Vbuf(), depfileset="rtl")
43+
self.add_depfileset(Vdffnq(), depfileset="rtl")
44+
self.add_depfileset(Vdffq(), depfileset="rtl")
3745
self.add_depfileset(Vinv(), depfileset="rtl")
46+
self.add_depfileset(Vlatnq(), depfileset="rtl")
47+
self.add_depfileset(Vlatq(), depfileset="rtl")
3848
self.add_depfileset(Vmux(), depfileset="rtl")
3949
self.add_depfileset(Vmux2(), depfileset="rtl")
4050
self.add_depfileset(Vmux2b(), depfileset="rtl")
@@ -44,4 +54,3 @@ def __init__(self):
4454
self.add_depfileset(Vmux6(), depfileset="rtl")
4555
self.add_depfileset(Vmux7(), depfileset="rtl")
4656
self.add_depfileset(Vmux8(), depfileset="rtl")
47-
self.add_depfileset(Vpriority(), depfileset="rtl")
Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
11
from lambdalib.lambdalib import Lambda
22

33

4-
class Vpriority(Lambda):
4+
class Vdffnq(Lambda):
55
def __init__(self):
6-
name = 'la_vpriority'
6+
name = 'la_vdffnq'
77
super().__init__(name, __file__)
88

99

1010
if __name__ == "__main__":
11-
d = Vpriority()
11+
d = Vdffnq()
1212
d.write_fileset(f"{d.name}.f", fileset="rtl")
Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
//#############################################################################
2+
//# Function: Vectorized negative edge-triggered static D-type flop-flop #
3+
//# Copyright: Lambda Project Authors. All rights Reserved. #
4+
//# License: MIT (see LICENSE file in Lambda repository) #
5+
//#############################################################################
6+
7+
module la_vdffnq #(parameter W = 1, // width of mux
8+
parameter PROP = "" // cell property
9+
)
10+
(
11+
input [W-1:0] d,
12+
input clk,
13+
output reg [W-1:0] q
14+
);
15+
16+
always @(negedge clk)
17+
q <= d;
18+
19+
endmodule
Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
from lambdalib.lambdalib import Lambda
2+
3+
4+
class Vdffq(Lambda):
5+
def __init__(self):
6+
name = 'la_vdffq'
7+
super().__init__(name, __file__)
8+
9+
10+
if __name__ == "__main__":
11+
d = Vdffq()
12+
d.write_fileset(f"{d.name}.f", fileset="rtl")
Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
//#############################################################################
2+
//# Function: Vectorized positive edge-triggered static D-type flop-flop #
3+
//# Copyright: Lambda Project Authors. All rights Reserved. #
4+
//# License: MIT (see LICENSE file in Lambda repository) #
5+
//#############################################################################
6+
7+
module la_vdffq #(parameter W = 1, // width of mux
8+
parameter PROP = "" // cell property
9+
)
10+
(
11+
input [W-1:0] d,
12+
input clk,
13+
output reg [W-1:0] q
14+
);
15+
16+
always @(posedge clk)
17+
q <= d;
18+
19+
endmodule
Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
from lambdalib.lambdalib import Lambda
2+
3+
4+
class Vlatnq(Lambda):
5+
def __init__(self):
6+
name = 'la_vlatnq'
7+
super().__init__(name, __file__)
8+
9+
10+
if __name__ == "__main__":
11+
d = Vlatnq()
12+
d.write_fileset(f"{d.name}.f", fileset="rtl")
Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,20 @@
1+
//#############################################################################
2+
//# Function: Vectorized D-type active-low transparent latch #
3+
//# Copyright: Lambda Project Authors. All rights Reserved. #
4+
//# License: MIT (see LICENSE file in Lambda repository) #
5+
//#############################################################################
6+
7+
module la_vlatnq #(parameter W = 1, // width of mux
8+
parameter PROP = "" // cell property
9+
)
10+
(
11+
input [W-1:0] d,
12+
input clk,
13+
output reg [W-1:0] q
14+
);
15+
16+
always @(clk or d)
17+
if (~clk)
18+
q <= d;
19+
20+
endmodule
Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
from lambdalib.lambdalib import Lambda
2+
3+
4+
class Vlatq(Lambda):
5+
def __init__(self):
6+
name = 'la_vlatq'
7+
super().__init__(name, __file__)
8+
9+
10+
if __name__ == "__main__":
11+
d = Vlatq()
12+
d.write_fileset(f"{d.name}.f", fileset="rtl")
Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,20 @@
1+
//#############################################################################
2+
//# Function: Vectorized D-type active-high transparent latch #
3+
//# Copyright: Lambda Project Authors. All rights Reserved. #
4+
//# License: MIT (see LICENSE file in Lambda repository) #
5+
//#############################################################################
6+
7+
module la_vlatq #(parameter W = 1, // width of mux
8+
parameter PROP = "" // cell property
9+
)
10+
(
11+
input [W-1:0] d,
12+
input clk,
13+
output reg [W-1:0] q
14+
);
15+
16+
always @ (clk or d)
17+
if (clk)
18+
q <= d;
19+
20+
endmodule

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