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Fix looping style
1 parent d7f9045 commit 24cd4de

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+14
-16
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+14
-16
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lambdalib/ramlib/la_tdpram/rtl/la_tdpram_impl.v

Lines changed: 14 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -56,27 +56,25 @@ module la_tdpram_impl #(
5656
reg [DW-1:0] ram[(2**AW)-1:0];
5757
/* verilator lint_on MULTIDRIVEN */
5858

59-
genvar i;
59+
integer i;
6060

61-
/* verilator lint_off MULTIDRIVEN */
62-
generate
61+
// Port A write
62+
always @(posedge clk_a) begin
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for (i = 0; i < DW; i = i + 1) begin
64-
// Port A write
65-
always @(posedge clk_a) begin
66-
if (ce_a && we_a && wmask_a[i]) begin
67-
ram[addr_a][i] <= din_a[i];
68-
end
69-
end
70-
// Port B write
71-
always @(posedge clk_b) begin
72-
if (ce_b && we_b && wmask_b[i]) begin
73-
ram[addr_b][i] <= din_b[i];
74-
end
64+
if (ce_a && we_a && wmask_a[i]) begin
65+
ram[addr_a][i] <= din_a[i];
7566
end
67+
end
68+
end
7669

70+
// Port B write
71+
always @(posedge clk_b) begin
72+
for (i = 0; i < DW; i = i + 1) begin
73+
if (ce_b && we_b && wmask_b[i]) begin
74+
ram[addr_b][i] <= din_b[i];
75+
end
7776
end
78-
endgenerate
79-
/* verilator lint_on MULTIDRIVEN */
77+
end
8078

8179
// Port A read
8280
always @(posedge clk_a) begin

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