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aolofssonaolofsson
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Reverting back to W parameter
- DW was confusing during use since muxes can be used for many different purposes, not just "datapath".
1 parent 2cea23b commit 8d9759b

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+131
-132
lines changed

10 files changed

+131
-132
lines changed

‎lambdalib/veclib/la_vbuf/rtl/la_vbuf.v‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,12 +4,12 @@
44
//# License: MIT (see LICENSE file in Lambda repository) #
55
//#############################################################################
66

7-
module la_vbuf #(parameter N = 1, // width of data inputs
7+
module la_vbuf #(parameter W = 1, // width of data inputs
88
parameter PROP = "DEFAULT" // custom cell property
99
)
1010
(
11-
input [N-1:0] a,
12-
output [N-1:0] z
11+
input [W-1:0] a,
12+
output [W-1:0] z
1313
);
1414

1515
assign z = a;

‎lambdalib/veclib/la_vinv/rtl/la_vinv.v‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4,13 +4,12 @@
44
//# License: MIT (see LICENSE file in Lambda repository) #
55
//#############################################################################
66

7-
module la_vinv #(
8-
parameter N = 1, // width of data inputs
7+
module la_vinv #(parameter W = 1, // width of data inputs
98
parameter PROP = "DEFAULT" // custom cell property
109
)
1110
(
12-
input [N-1:0] a,
13-
output [N-1:0] z
11+
input [W-1:0] a,
12+
output [W-1:0] z
1413
);
1514

1615
assign z = ~a;

‎lambdalib/veclib/la_vmux/rtl/la_vmux.v‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -5,20 +5,20 @@
55
//############################################################################
66

77
module la_vmux #(parameter N = 1, // number of ports
8-
parameter DW = 1, // data width
8+
parameter W = 1, // data width
99
parameter PROP = "DEFAULT" // cell property
1010
)
1111
(
12-
input [N-1:0] sel, // select vector
13-
input [DW*N-1:0] in, // flattened input {.., in1[DW-1:0],in0[DW-1:0]}
14-
output reg [DW-1:0] out // output
12+
input [N-1:0] sel, // select vector
13+
input [W*N-1:0] in, // flattened input {.., in1[W-1:0],in0[W-1:0]}
14+
output reg [W-1:0] out // output
1515
);
1616

1717
integer i;
1818
always @* begin
19-
out[DW-1:0] = 'b0;
19+
out[W-1:0] = 'b0;
2020
for (i = 0; i < N; i = i + 1)
21-
out[DW-1:0] = out[DW-1:0] | {(DW) {sel[i]}} & in[i*DW+:DW];
21+
out[W-1:0] = out[W-1:0] | {(W) {sel[i]}} & in[i*W+:W];
2222
end
2323

2424
// TODO: Add One hot warning

‎lambdalib/veclib/la_vmux2/rtl/la_vmux2.v‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -4,18 +4,18 @@
44
//# License: MIT (see LICENSE file in Lambda repository) #
55
//############################################################################
66

7-
module la_vmux2 #(parameter DW = 1, // width of mux
7+
module la_vmux2 #(parameter W = 1, // width of mux
88
parameter PROP = "DEFAULT" // cell property
99
)
1010
(
11-
input sel1,
12-
input sel0,
13-
input [DW-1:0] in1,
14-
input [DW-1:0] in0,
15-
output [DW-1:0] out
11+
input sel1,
12+
input sel0,
13+
input [W-1:0] in1,
14+
input [W-1:0] in0,
15+
output [W-1:0] out
1616
);
1717

18-
assign out[DW-1:0] = ({(DW) {sel0}} & in0[DW-1:0] |
19-
{(DW) {sel1}} & in1[DW-1:0]);
18+
assign out[W-1:0] = ({(W) {sel0}} & in0[W-1:0] |
19+
{(W) {sel1}} & in1[W-1:0]);
2020

2121
endmodule

‎lambdalib/veclib/la_vmux3/rtl/la_vmux3.v‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -4,21 +4,21 @@
44
//# License: MIT (see LICENSE file in Lambda repository) #
55
//############################################################################
66

7-
module la_vmux3 #(parameter DW = 1, // width of mux
7+
module la_vmux3 #(parameter W = 1, // width of mux
88
parameter PROP = "DEFAULT" // cell property
99
)
1010
(
11-
input sel2,
12-
input sel1,
13-
input sel0,
14-
input [DW-1:0] in2,
15-
input [DW-1:0] in1,
16-
input [DW-1:0] in0,
17-
output [DW-1:0] out
11+
input sel2,
12+
input sel1,
13+
input sel0,
14+
input [W-1:0] in2,
15+
input [W-1:0] in1,
16+
input [W-1:0] in0,
17+
output [W-1:0] out
1818
);
1919

20-
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
21-
{(DW){sel1}} & in1[DW-1:0] |
22-
{(DW){sel2}} & in2[DW-1:0]);
20+
assign out[W-1:0] = ({(W){sel0}} & in0[W-1:0] |
21+
{(W){sel1}} & in1[W-1:0] |
22+
{(W){sel2}} & in2[W-1:0]);
2323

2424
endmodule

‎lambdalib/veclib/la_vmux4/rtl/la_vmux4.v‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -4,24 +4,24 @@
44
//# License: MIT (see LICENSE file in Lambda repository) #
55
//############################################################################
66

7-
module la_vmux4 #(parameter DW = 1, // width of mux
7+
module la_vmux4 #(parameter W = 1, // width of mux
88
parameter PROP = "DEFAULT" // cell property
99
)
1010
(
11-
input sel3,
12-
input sel2,
13-
input sel1,
14-
input sel0,
15-
input [DW-1:0] in3,
16-
input [DW-1:0] in2,
17-
input [DW-1:0] in1,
18-
input [DW-1:0] in0,
19-
output [DW-1:0] out
11+
input sel3,
12+
input sel2,
13+
input sel1,
14+
input sel0,
15+
input [W-1:0] in3,
16+
input [W-1:0] in2,
17+
input [W-1:0] in1,
18+
input [W-1:0] in0,
19+
output [W-1:0] out
2020
);
2121

22-
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
23-
{(DW){sel1}} & in1[DW-1:0] |
24-
{(DW){sel2}} & in2[DW-1:0] |
25-
{(DW){sel3}} & in3[DW-1:0]);
22+
assign out[W-1:0] = ({(W){sel0}} & in0[W-1:0] |
23+
{(W){sel1}} & in1[W-1:0] |
24+
{(W){sel2}} & in2[W-1:0] |
25+
{(W){sel3}} & in3[W-1:0]);
2626

2727
endmodule

‎lambdalib/veclib/la_vmux5/rtl/la_vmux5.v‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -4,27 +4,27 @@
44
//# License: MIT (see LICENSE file in Lambda repository) #
55
//############################################################################
66

7-
module la_vmux5 #(parameter DW = 1, // width of mux
7+
module la_vmux5 #(parameter W = 1, // width of mux
88
parameter PROP = "DEFAULT" // cell property
99
)
1010
(
11-
input sel4,
12-
input sel3,
13-
input sel2,
14-
input sel1,
15-
input sel0,
16-
input [DW-1:0] in4,
17-
input [DW-1:0] in3,
18-
input [DW-1:0] in2,
19-
input [DW-1:0] in1,
20-
input [DW-1:0] in0,
21-
output [DW-1:0] out
11+
input sel4,
12+
input sel3,
13+
input sel2,
14+
input sel1,
15+
input sel0,
16+
input [W-1:0] in4,
17+
input [W-1:0] in3,
18+
input [W-1:0] in2,
19+
input [W-1:0] in1,
20+
input [W-1:0] in0,
21+
output [W-1:0] out
2222
);
2323

24-
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
25-
{(DW){sel1}} & in1[DW-1:0] |
26-
{(DW){sel2}} & in2[DW-1:0] |
27-
{(DW){sel3}} & in3[DW-1:0] |
28-
{(DW){sel4}} & in4[DW-1:0]);
24+
assign out[W-1:0] = ({(W){sel0}} & in0[W-1:0] |
25+
{(W){sel1}} & in1[W-1:0] |
26+
{(W){sel2}} & in2[W-1:0] |
27+
{(W){sel3}} & in3[W-1:0] |
28+
{(W){sel4}} & in4[W-1:0]);
2929

3030
endmodule

‎lambdalib/veclib/la_vmux6/rtl/la_vmux6.v‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -4,30 +4,30 @@
44
//# License: MIT (see LICENSE file in Lambda repository) #
55
//############################################################################
66

7-
module la_vmux6 #(parameter DW = 1, // width of mux
7+
module la_vmux6 #(parameter W = 1, // width of mux
88
parameter PROP = "DEFAULT" // cell property
99
)
1010
(
11-
input sel5,
12-
input sel4,
13-
input sel3,
14-
input sel2,
15-
input sel1,
16-
input sel0,
17-
input [DW-1:0] in5,
18-
input [DW-1:0] in4,
19-
input [DW-1:0] in3,
20-
input [DW-1:0] in2,
21-
input [DW-1:0] in1,
22-
input [DW-1:0] in0,
23-
output [DW-1:0] out //selected data output
11+
input sel5,
12+
input sel4,
13+
input sel3,
14+
input sel2,
15+
input sel1,
16+
input sel0,
17+
input [W-1:0] in5,
18+
input [W-1:0] in4,
19+
input [W-1:0] in3,
20+
input [W-1:0] in2,
21+
input [W-1:0] in1,
22+
input [W-1:0] in0,
23+
output [W-1:0] out //selected data output
2424
);
2525

26-
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
27-
{(DW){sel1}} & in1[DW-1:0] |
28-
{(DW){sel2}} & in2[DW-1:0] |
29-
{(DW){sel3}} & in3[DW-1:0] |
30-
{(DW){sel4}} & in4[DW-1:0] |
31-
{(DW){sel5}} & in5[DW-1:0]);
26+
assign out[W-1:0] = ({(W){sel0}} & in0[W-1:0] |
27+
{(W){sel1}} & in1[W-1:0] |
28+
{(W){sel2}} & in2[W-1:0] |
29+
{(W){sel3}} & in3[W-1:0] |
30+
{(W){sel4}} & in4[W-1:0] |
31+
{(W){sel5}} & in5[W-1:0]);
3232

3333
endmodule

‎lambdalib/veclib/la_vmux7/rtl/la_vmux7.v‎

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -4,33 +4,33 @@
44
//# License: MIT (see LICENSE file in Lambda repository) #
55
//############################################################################
66

7-
module la_vmux7 #(parameter DW = 1, // width of mux
7+
module la_vmux7 #(parameter W = 1, // width of mux
88
parameter PROP = "DEFAULT" // cell property
99
)
1010
(
11-
input sel6,
12-
input sel5,
13-
input sel4,
14-
input sel3,
15-
input sel2,
16-
input sel1,
17-
input sel0,
18-
input [DW-1:0] in6,
19-
input [DW-1:0] in5,
20-
input [DW-1:0] in4,
21-
input [DW-1:0] in3,
22-
input [DW-1:0] in2,
23-
input [DW-1:0] in1,
24-
input [DW-1:0] in0,
25-
output [DW-1:0] out
11+
input sel6,
12+
input sel5,
13+
input sel4,
14+
input sel3,
15+
input sel2,
16+
input sel1,
17+
input sel0,
18+
input [W-1:0] in6,
19+
input [W-1:0] in5,
20+
input [W-1:0] in4,
21+
input [W-1:0] in3,
22+
input [W-1:0] in2,
23+
input [W-1:0] in1,
24+
input [W-1:0] in0,
25+
output [W-1:0] out
2626
);
2727

28-
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
29-
{(DW){sel1}} & in1[DW-1:0] |
30-
{(DW){sel2}} & in2[DW-1:0] |
31-
{(DW){sel3}} & in3[DW-1:0] |
32-
{(DW){sel4}} & in4[DW-1:0] |
33-
{(DW){sel5}} & in5[DW-1:0] |
34-
{(DW){sel6}} & in6[DW-1:0]);
28+
assign out[W-1:0] = ({(W){sel0}} & in0[W-1:0] |
29+
{(W){sel1}} & in1[W-1:0] |
30+
{(W){sel2}} & in2[W-1:0] |
31+
{(W){sel3}} & in3[W-1:0] |
32+
{(W){sel4}} & in4[W-1:0] |
33+
{(W){sel5}} & in5[W-1:0] |
34+
{(W){sel6}} & in6[W-1:0]);
3535

3636
endmodule

‎lambdalib/veclib/la_vmux8/rtl/la_vmux8.v‎

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -4,36 +4,36 @@
44
//# License: MIT (see LICENSE file in Lambda repository) #
55
//############################################################################
66

7-
module la_vmux8 #(parameter DW = 1, // width of mux
7+
module la_vmux8 #(parameter W = 1, // width of mux
88
parameter PROP = "DEFAULT" // cell property
99
)
1010
(
11-
input sel7,
12-
input sel6,
13-
input sel5,
14-
input sel4,
15-
input sel3,
16-
input sel2,
17-
input sel1,
18-
input sel0,
19-
input [DW-1:0] in7,
20-
input [DW-1:0] in6,
21-
input [DW-1:0] in5,
22-
input [DW-1:0] in4,
23-
input [DW-1:0] in3,
24-
input [DW-1:0] in2,
25-
input [DW-1:0] in1,
26-
input [DW-1:0] in0,
27-
output [DW-1:0] out
11+
input sel7,
12+
input sel6,
13+
input sel5,
14+
input sel4,
15+
input sel3,
16+
input sel2,
17+
input sel1,
18+
input sel0,
19+
input [W-1:0] in7,
20+
input [W-1:0] in6,
21+
input [W-1:0] in5,
22+
input [W-1:0] in4,
23+
input [W-1:0] in3,
24+
input [W-1:0] in2,
25+
input [W-1:0] in1,
26+
input [W-1:0] in0,
27+
output [W-1:0] out
2828
);
2929

30-
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
31-
{(DW){sel1}} & in1[DW-1:0] |
32-
{(DW){sel2}} & in2[DW-1:0] |
33-
{(DW){sel3}} & in3[DW-1:0] |
34-
{(DW){sel4}} & in4[DW-1:0] |
35-
{(DW){sel5}} & in5[DW-1:0] |
36-
{(DW){sel6}} & in6[DW-1:0] |
37-
{(DW){sel7}} & in7[DW-1:0]);
30+
assign out[W-1:0] = ({(W){sel0}} & in0[W-1:0] |
31+
{(W){sel1}} & in1[W-1:0] |
32+
{(W){sel2}} & in2[W-1:0] |
33+
{(W){sel3}} & in3[W-1:0] |
34+
{(W){sel4}} & in4[W-1:0] |
35+
{(W){sel5}} & in5[W-1:0] |
36+
{(W){sel6}} & in6[W-1:0] |
37+
{(W){sel7}} & in7[W-1:0]);
3838

3939
endmodule

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