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1 | 1 | # Lambdalib Introduction |
2 | 2 |
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3 | | -Lambdalib is a modular hardware abstraction library which decouples design from the underlying manufacturing target. Lambdalib defines a set of generic functions that get resolved during the target technology mapping stage. |
| 3 | +Lambdalib is a modular hardware abstraction library which decouples design from the manufacturing target. The project was inspired by the `Lambda` concept invented during the [1978 VLSI revolution by Mead and Conway](https://en.wikipedia.org/wiki/Mead%E2%80%93Conway_VLSI_chip_design_revolution). |
4 | 4 |
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5 | | -Lambdalib includes the following hardware categories: |
| 5 | +The original single value Lambda approach no longer applies to modern CMOS manufacturing, so Lambdalib has raised the abstraction level to the cell/block level to enable automated porting between compilation targets. |
| 6 | + |
| 7 | +Lambdalib abstracts away technology specific design modules that cannot be cleanly expressed in technology agnostic RTL Verilog code (eg. synchronizers, analog circuits, io cells, etc.) |
| 8 | + |
| 9 | +The table below summarizes the categories of cells available. |
6 | 10 |
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7 | 11 | | Category | Description | |
8 | 12 | |-------------------------------------|---------------------------------------| |
9 | | -|[stdlib](lambdalib/stdlib/rtl) | Standard library cells (inv, nand, ff, ...) |
10 | | -|[auxlib](lambdalib/auxlib/rtl) | Special library cells (antenna, decap, clkmux,...) |
| 13 | +|[stdlib](lambdalib/stdlib/rtl) | Standard cells (inv, nand, ff, ...) |
| 14 | +|[auxlib](lambdalib/auxlib/rtl) | Special cells (antenna, decap, clkmux,...) |
11 | 15 | |[ramlib](lambdalib/ramlib/rtl) | Memory (single port, dual port, fifo, ...) |
12 | 16 | |[iolib](lambdalib/iolib) | IO cells (bidir, vdd, clamp,...) |
13 | 17 | |[padring](lambdalib/padring) | Padring generator |
14 | | -|[vectorlib](lambdalib/vecib/rtl) | Vectorized library (mux, isolation) |
| 18 | +|[veclib](lambdalib/veclib/rtl) | Vectorized datapath cells (mux, buf,..) |
15 | 19 | |[fpgalib](lambdalib/fpgalib/rtl) | FPGA cells (lut4, ble, clb) |
16 | 20 |
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17 | 21 | The [Lambdapdk](https://github.com/siliconcompiler/lambdapdk) repository demonstrates implementation of the Lambdalib interfaces across a number of open source process technologies. |
18 | 22 |
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19 | 23 | Lambdalib has been successfully used in multiple tapeouts using [SiliconCompiler](https://github.com/siliconcompiler/siliconcompiler). |
20 | 24 |
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21 | | - |
22 | 25 | # Installation |
23 | 26 |
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24 | | -```sh |
25 | | -git clone https://github.com/siliconcompiler/lambdalib |
| 27 | +```bash |
| 28 | +git clone https://github.com/zeroasiccorp/lambdalib |
26 | 29 | cd lambdalib |
27 | | -python3 -m pip install -e . # Local install |
28 | | -python3 -m pip install -e .[docs,test] # Optional step for generating docs and running tests |
| 30 | +pip install --upgrade pip |
| 31 | +pip install -e . |
29 | 32 | ``` |
30 | 33 |
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31 | 34 | # Examples |
32 | 35 |
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33 | | -The following example illustrate lambdalib use models |
34 | | - |
35 | 36 | ## Instantiating a Lambdalib module |
36 | 37 |
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37 | | -This example shows how to instatiate the Padring module in a top level chip design. |
| 38 | +This example shows how to instantiate the Padring module in a top level chip design. |
38 | 39 | We could have chosen any module to instantiate (inverter, flip flop, dual port ram...). |
39 | 40 |
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40 | 41 |
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