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Pretty much every single ARM platformm that we want to support uses PSCI for booting secondary cores, except for Rasberry Pi 4B which uses a spin-table mechanism. Signed-off-by: Ivan Velickovic <i.velickovic@unsw.edu.au>
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| *release_addr = (uint64_t)arm_spin_table_secondary_cpu_entry_asm; | ||
| /* Ensure that the write to release address occurs before waking up the secondary CPU. */ | ||
| asm volatile("dsb sy" ::: "memory"); |
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The dsb can also be explained using the following text from Arm ARM:
$\textsf{I}_\textsf{DVZXD}$ Arm recommends that software includes aDSBinstruction before anySEVinstruction.DSBinstruction ensures that no instructions, including anySEVinstructions, that appear in program order after theDSBinstruction, can execute until theDSBinstruction has completed
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I would also say "finishes" instead of "occurs", as that is more explicit.
(Cool, I couldn't figure out a way to do those subscripts for Arm references, now I know how.)
| * For the moment this code assumes that CPUs are booted using the ARM PSCI | ||
| * standard. We reference Version 1.3 issue F.b. | ||
| * Most of this code that CPUs are booted using the ARM PSCI standard. | ||
| * We reference Version 1.3 issue F.b. |
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What are you trying to say here?
"For booting CPUs with PSCI we reference Verions 1.3 issue F.b of the Arm PSCI standard."?
But if you keep the "Most of this code assumes" bit, it would make more sense to have it at the top of the file.
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| *release_addr = (uint64_t)arm_spin_table_secondary_cpu_entry_asm; | ||
| /* Ensure that the write to release address occurs before waking up the secondary CPU. */ | ||
| asm volatile("dsb sy" ::: "memory"); |
There was a problem hiding this comment.
I would also say "finishes" instead of "occurs", as that is more explicit.
(Cool, I couldn't figure out a way to do those subscripts for Arm references, now I know how.)
Pretty much every single ARM platform that we want to support uses PSCI for booting secondary cores, except for Raspberry Pi 4B which uses a spin-table mechanism.
TODO:
Closes #401.