`core::num::f16b` Rust's 16bit Brain Float by Jamesbarford · Pull Request #160859 · rust-lang/rust

Jamesbarford · 2026-08-10T14:27:46Z

Implements the RFC: f16b type. Best reviewed commit by commit, happy to split into separate PRs if that is deemed easier to review. However the line count and surface area is, in my opinion, reasonably small.

Adds;

ABI plumbing for the f16b along with bfloat lang item to work with LLVM, GCC is explicitly unimplemented!(...)
f16b feature gate, page for f16b on libruscdoc and a struct bf16 in core::num
Tests
Treat f16b as a scalar primitive for scalable vectors

Issues;

rustbot · 2026-08-10T14:27:50Z

Some changes occurred in compiler/rustc_attr_ir

cc @jdonszelmann, @JonathanBrouwer

This PR changes rustc_public

cc @oli-obk, @celinval, @ouz-a, @makai410

rustc_codegen_gcc is developed in its own repository. If possible, consider making this change to rust-lang/rustc_codegen_gcc instead.

cc @antoyo, @GuillaumeGomez

rustbot · 2026-08-10T14:27:54Z

r? @jieyouxu

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jieyouxu · 2026-08-10T14:45:34Z

@rustbot reroll

antoyo · 2026-08-10T14:48:39Z

    }

+    fn type_f16b(&self) -> Type<'gcc> {
+        bug!("f16b is not supported by the GCC codegen backend")


I believe GCC actually supports this type: https://github.com/rust-lang/gccjit.rs/blob/master/src/context.rs#L1482

View changes since the review

Thanks 😄, I will aim to add it in a follow up PR 👍

Actually, as @folkertdev pointed out, it was a doddle. So I've included the implementation in the PR 👍

rustbot · 2026-08-10T14:48:49Z

rustc_codegen_cranelift is developed in its own repository. If possible, consider making this change to rust-lang/rustc_codegen_cranelift instead.

cc @bjorn3

bjorn3 · 2026-08-10T14:54:16Z

What is the calling convention of other targets?

View changes since the review

I believe only these files were changed because they have an exhaustive match on Float.

However, my version of abi-cafe found two interesting failures: GCC and Clang are inconsistent on aarch64 and armv7

// callee, compiled with GCC 12 #include <inttypes.h> #include <string.h> #include <stdio.h> #include <stdbool.h> typedef struct Many1 { __bf16 f0; } Many1; void struct_in_1(Many1 arg0) { printf("%d", arg0.f0); }

// caller, compiled with clang 23 #include <inttypes.h> #include <string.h> #include <stdio.h> #include <stdbool.h> typedef struct Many1 { __bf16 f0; } Many1; void struct_in_1(Many1 arg0); void do_test(void) { { Many1 arg0 = { .f0 = (((union { uint16_t bits; __bf16 value; }){ .bits = 49600 }).value) }; printf("%d", arg0.f0); struct_in_1(arg0); } }

hits

func struct_in_1's values differed values (native-endian hex bytes): expect: C0 C1 caller: C0 C1 callee: 04 00 the value was arg0.f0: rustarithmeticty(f16b) whose arg was arg0: Many1

The current Rust implementation matches clang, and is hence incompatible with GCC

armv7 with hardware floats also runs into incompatibilities

[target.armv7-unknown-linux-gnueabihf."f16::conv_c::repr_c::clang-nightly_calls_distro-gcc"] busted = "check" [target.armv7-unknown-linux-gnueabihf."f16::conv_c::repr_c::distro-gcc_calls_clang-nightly"] busted = "check" [target.armv7-unknown-linux-gnueabihf."f16b::conv_c::repr_c::clang-nightly_calls_distro-gcc"] busted = "check" [target.armv7-unknown-linux-gnueabihf."f16b::conv_c::repr_c::distro-gcc_calls_clang-nightly"] busted = "check"

Finally, you can let this ICE on many targets, e.g. mips, powerpc, s390x, sparc

https://godbolt.org/z/ox3G88hEW

You can also (e.g. on loongarch64 https://godbolt.org/z/Y3hdhG4e6) emit a __truncsfbf2 libcall that is not provided (probably needs to be added to compiler-builtins).

I think the ICEs are probably a blocker? That needs a mechanism similar to has_reliable_f128.

Yes I added it because of the exhaustive match statement in mips64.rs and sparc64.rs I've removed it; 40d3f6e and put in a panic!(...).

With regard to has_reliable_f128, are you envisaging a has_reliable_f16b entry on TargetConfig?

With regard to has_reliable_f128, are you envisaging a has_reliable_f16b entry on TargetConfig?

Exactly

What's your take on those ABI mismatches? We should track that somewhere.

I'm not particularly certain what mips64 should do.

It doesn't, at least to my knowledge, have hardware support. Given we aren't implementing scalar arithmetic and an f16b can only be created through a bit pattern or vendor intrinsics, I can't immediately see a practical application? Hence a panic! seems like a pragmatic choice for the time being.

No comment on whether this is the right approach, but always use span_bug! or at least bug! where possible in the compiler, rather than panic. It gives much more useful info.

We can't use those custom macros in rustc_target because they are defined in rustc_middle, and that crate depends on rustc_target.

It doesn't seem possible to use in compiler/rustc_target, however elsewhere I have strived to use it when available.

folkertdev · 2026-08-11T13:50:33Z

I believe only these files were changed because they have an exhaustive match on Float.

However, my version of abi-cafe found two interesting failures: GCC and Clang are inconsistent on aarch64 and armv7

// callee, compiled with GCC 12 #include <inttypes.h> #include <string.h> #include <stdio.h> #include <stdbool.h> typedef struct Many1 { __bf16 f0; } Many1; void struct_in_1(Many1 arg0) { printf("%d", arg0.f0); }

// caller, compiled with clang 23 #include <inttypes.h> #include <string.h> #include <stdio.h> #include <stdbool.h> typedef struct Many1 { __bf16 f0; } Many1; void struct_in_1(Many1 arg0); void do_test(void) { { Many1 arg0 = { .f0 = (((union { uint16_t bits; __bf16 value; }){ .bits = 49600 }).value) }; printf("%d", arg0.f0); struct_in_1(arg0); } }

hits

func struct_in_1's values differed values (native-endian hex bytes): expect: C0 C1 caller: C0 C1 callee: 04 00 the value was arg0.f0: rustarithmeticty(f16b) whose arg was arg0: Many1

The current Rust implementation matches clang, and is hence incompatible with GCC

armv7 with hardware floats also runs into incompatibilities

[target.armv7-unknown-linux-gnueabihf."f16::conv_c::repr_c::clang-nightly_calls_distro-gcc"] busted = "check" [target.armv7-unknown-linux-gnueabihf."f16::conv_c::repr_c::distro-gcc_calls_clang-nightly"] busted = "check" [target.armv7-unknown-linux-gnueabihf."f16b::conv_c::repr_c::clang-nightly_calls_distro-gcc"] busted = "check" [target.armv7-unknown-linux-gnueabihf."f16b::conv_c::repr_c::distro-gcc_calls_clang-nightly"] busted = "check"

Finally, you can let this ICE on many targets, e.g. mips, powerpc, s390x, sparc

https://godbolt.org/z/ox3G88hEW

rustbot · 2026-08-12T12:03:56Z

Some changes occurred in cfg and check-cfg configuration

cc @Urgau

miri is developed in its own repository. If the Miri part of this change can be broken out, consider making this change to rust-lang/miri instead. However, if Miri needs adjusting for rustc changes, just ignore this message.

cc @rust-lang/miri

mati865 · 2026-08-12T13:36:14Z

I'm not a good reviewer for this change. Can somebody here pick it up rather than blindly rerolling?

folkertdev · 2026-08-12T13:54:02Z

r? me

tgross35 · 2026-09-01T19:30:36Z

Guess some jobs got renamed...

@bors try jobs=test-various,aarch64-apple-,-gnu-nopt-,x86_64-mingw-,aarch64-msvc-*,arm-android

`core::num::f16b` Rust's 16bit Brain Float try-job: test-various try-job: aarch64-apple-* try-job: *-gnu-nopt-* try-job: x86_64-mingw-* try-job: aarch64-msvc-* try-job: arm-android

folkertdev · 2026-09-01T21:34:04Z

Oh fun I hit https://triage.rust-lang.org/gha-logs/rust-lang/rust/99996805056 before, the issue is some symbol being bumped and now being 3 digits instead of 2, causing formatting changes.

tgross35 · 2026-09-02T09:53:51Z

@bors try jobs=test-various,aarch64-apple-,-gnu-nopt-,x86_64-mingw-,aarch64-msvc-*,arm-android

`core::num::f16b` Rust's 16bit Brain Float try-job: test-various try-job: aarch64-apple-* try-job: *-gnu-nopt-* try-job: x86_64-mingw-* try-job: aarch64-msvc-* try-job: arm-android

rust-bors · 2026-09-02T12:23:37Z

💔 Test for f6d6327 failed: CI. Failed jobs:

try - aarch64-apple-1 (web logs, enhanced plaintext logs)
try - aarch64-apple-macos-26-1 (web logs, enhanced plaintext logs)
try - aarch64-msvc-1 (web logs, enhanced plaintext logs)
try - arm-android (web logs, enhanced plaintext logs)
try - i686-gnu-nopt-1 (web logs, enhanced plaintext logs)
(and 2 other jobs)

@folkertdev

…lkertdev Make sin, cos, exp, exp2, log, log2, log10 generic Rebased and smaller version of rust-lang/rust#153934 Following `fabs`, make the `sin`, `cos`, `exp`, `exp2`, `log`, `log2` and `log10` intrinsics generic over the float type, rather than having four variants per float type. The first two commits are purely stylistic: - reorganised Cranelift code to make following changes simpler - moved a misplaced comment in `compiler/rustc_codegen_llvm/src/intrinsic.rs` that caused `x fmt` to give up The last commit actually makes them generic! Most code is a bit simpler, ~~and this will also hopefully simplify adding support for these intrinsics for the future [`bf16` type](rust-lang/rust#160859 :) Unfortunately both GCC and Cranelift backend changes are a bit churny. Their code is a bit, opaque, to put it kindly, and I didn't want to refactor those here. r? @folkertdev cc @RalfJung

update tests and remove major >= 21 check

… in the documentation

rustbot · 2026-09-02T13:25:32Z

This PR was rebased onto a different main commit. Here's a range-diff highlighting what actually changed.

Rebasing is a normal part of keeping PRs up to date, so no action is needed—this note is just to help reviewers.

rustbot added A-attributes Area: Attributes (`#[…]`, `#![…]`) A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels Aug 10, 2026

rustbot assigned jieyouxu Aug 10, 2026

rustbot added T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. T-libs Relevant to the library team, which will review and decide on the PR/issue. labels Aug 10, 2026

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antoyo reviewed Aug 10, 2026

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Jamesbarford force-pushed the feat/fb16-pt1 branch from bf10f8a to 01c5c1b Compare August 10, 2026 14:48

bjorn3 reviewed Aug 10, 2026

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Comment thread compiler/rustc_ty_utils/src/layout.rs

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Comment thread library/core/src/num/f16b.rs Outdated

Comment thread library/core/src/num/bfloat.rs

Comment thread tests/codegen-llvm/float/f16b.rs Outdated

Jamesbarford force-pushed the feat/fb16-pt1 branch from 53d3660 to 40d3f6e Compare August 12, 2026 08:19

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rustbot added the A-test-infra-minicore Area: `minicore` test auxiliary and `//@ add-core-stubs` label Aug 12, 2026

Jamesbarford force-pushed the feat/fb16-pt1 branch from da620d0 to 0ed984f Compare August 12, 2026 10:08

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Comment thread tests/assembly-llvm/f16b.rs

folkertdev mentioned this pull request Sep 1, 2026

add IBM f128 type #162156

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rustbot added A-tidy Area: The tidy tool T-bootstrap Relevant to the bootstrap subteam: Rust's build system (x.py and src/bootstrap) labels Sep 2, 2026

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Jamesbarford added 9 commits September 2, 2026 14:25

Create f16b struct and documentation

b8e8192

Add F16B to Float & wireup trivial matches

4d5b9af

Use cfg's in backends

311f257

Wire up backends

ad0b6b6

Create tests

e17918f

cfg test on target_has_reliable_f16b

eb51279

Consolidate assembly-llvm tests into one, factor out ignore's,

82f3b2b

update tests and remove major >= 21 check

Test changes for Tidy, hard cfg check and include the use core...…

8e77c77

… in the documentation

add optimisation revisions for scalable-vectors/bf16-intrinsic.rs test

39a366b

Jamesbarford force-pushed the feat/fb16-pt1 branch from c7fcc75 to 39a366b Compare September 2, 2026 13:25

rename brain_float bfloat

8d69ed1

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