perf(gpu): use an integer tree for trimmed ICP selection

[rsasaki0109]

The capable-device Trimmed ICP selector previously walked up to 256 histogram bins on one lane. Build an exact shared integer sum tree and select each byte/within-bin rank with eight decisions; retain the existing small/device-limited 64-lane linear route. Global scratch, digit passes, selected pairs, moment math and explicit transfers remain unchanged. The wide selector accesses 2 KiB shared storage under the existing limit and adds eight barriers.

Two isolated completed-call surveys retain every adverse case. Fully gated 65,537-point prepared synthetic moments improve 1.045x and 1.052x with within-survey intervals above one. Standalone selector intervals include one; other prepared/full results are mixed, including a small full-call regression. This does not establish general selector, registration or device-wide acceleration. Details and all 40 rows are in notes/2026-10-13_gpu_icp_trim_selection_tree.md.

Validation:

• 210 stable-sort selection conditions match frozen PR Reduce resident GPU Canny gradient memory by half #181/Parallelize resident GPU ICP trim histogram selection #182 GPU routes; 7,168 maximum-mass digit words and 65,536 all-bin rank-endpoint words agree with independent integer references.
• GPU point/image-kernel regression: 144 passed, zero failed, 15 measurement fixtures ignored; native trim family: 14 passed, two measurements ignored.
• Five release registration tests explicitly include GPU cases: 486 reference conditions and 27 large trajectories preserve the original pose thresholds. The historical PR Reduce resident GPU Canny gradient memory by half #181/Parallelize resident GPU ICP trim histogram selection #182 paired survey also runs against actual frozen pipelines.
• GPU all-feature/all-target Clippy, feature-free GPU, GPU-image WASM, minimal register-icp-gpu facade and formatting checks pass. WASM execution was not measured.