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95a694a
[SRC] Change cluster base id to a paramemter instead of a logic input…
DiyouS Aug 17, 2026
e5aa7e5
[Util] Add missing yaml package into venv, and fix a hardcoded path i…
DiyouS Aug 17, 2026
357a6db
[SRC] Rename paraemter NumCore to NumCC
DiyouS Aug 18, 2026
92a0e48
[SRC] WIP: add dual-snitch basic hardware (not yet enabled)
DiyouS Aug 18, 2026
c6b7f5d
[SRC] Add the dual-scalar core hardware
DiyouS Aug 19, 2026
7986874
[CFG] Add dual scalar core configuration for testing
DiyouS Aug 19, 2026
32c2949
[SW] Add needed runtime functions to support dual-scalar core configu…
DiyouS Aug 19, 2026
cd3a5e6
[SW] Add missing makefile for configuration
DiyouS Aug 19, 2026
e09e462
[Makefile] Update venv environment to force python3.12. Update makefi…
DiyouS Aug 19, 2026
5728dd2
[Makefile] Update makefile targets
DiyouS Aug 20, 2026
7ae10e7
[SW] Add new test for dual scalar core. Fix bug accordingly
DiyouS Aug 20, 2026
e2f40db
[SW] Reconstruct software kernel folder to place them in better locat…
DiyouS Aug 24, 2026
d755220
[SRC] Update FSM implementation to have a cleaner result informing an…
DiyouS Aug 25, 2026
ce40785
[SRC] Fix a bug in Spatz related to dual-scalar core muxing. Add synt…
DiyouS Aug 25, 2026
5b24159
[SRC] Fix a bug in loading instruction handling for dual-scalar core
DiyouS Aug 26, 2026
2c8b4f5
[SW] Adapt the kernels for dual scalar core configuration.
DiyouS Aug 27, 2026
45b99f9
[CI] Add dual-scalar core configuration into CI and limit the thread …
DiyouS Aug 27, 2026
8c89b98
[CI] Add a manual CI run target on the 16g configuration
DiyouS Aug 28, 2026
c771eb5
[CI] Fix the skipped CI test
DiyouS Aug 28, 2026
3e6b9a2
[Makefile] Add clean floonoc into clean.hw, to make sure noc configur…
DiyouS Aug 28, 2026
d51e1ad
[CI] Remove two tests that run too long for largest configuration
DiyouS Aug 28, 2026
bc435c6
[SRC] Clean: remove unused cluster interrupt port
DiyouS Aug 31, 2026
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123 changes: 121 additions & 2 deletions .gitlab-ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,9 @@ variables:
python3: 'python3'
# Config to build and test
CI_CONFIG: 'cachepool_fpu_4g'
SW_PREFIX: 'test-cachepool-'
CI_CONFIG_DUAL: 'cachepool_dual_fpu_4g'
CI_CONFIG_16G: 'cachepool_fpu_16g'
SW_PREFIX: 'test-'

default:
tags: [shared]
Expand Down Expand Up @@ -60,6 +62,63 @@ build:
- hardware/deps/dram_rtl_sim/dramsys_lib/DRAMSys/build/lib/
- hardware/deps/dram_rtl_sim/dramsys_lib/DRAMSys/configs/

# ---------------------------------------------------------------------------
# Build stage: same as `build`, for the dual-scalar-per-CC config. Only the
# kernels adapted for dual-scalar (see `test-dual`) are exercised against it.
# ---------------------------------------------------------------------------
build-dual:
stage: build
script:
- echo "Using CC=$CC"
- echo "Using CXX=$CXX"
- test -x "$CC"
- test -x "$CXX"
- source iis-env.sh
- make init
- make dram-build
- make clean generate update-floonoc bootrom vsim sw config=$CI_CONFIG_DUAL DEBUG=0 noc_profiling=0
artifacts:
when: always
expire_in: 2h
paths:
- sim/work/
- sim/bin/cachepool_cluster.vsim
- sim/bin/cachepool_cluster.vsim.gui
- sim/work-dpi/
- software/build/CachePoolTests/
- hardware/deps/dram_rtl_sim/dramsys_lib/DRAMSys/build/lib/
- hardware/deps/dram_rtl_sim/dramsys_lib/DRAMSys/configs/

# ---------------------------------------------------------------------------
# Build stage: same as `build`, for the largest available config (16 groups).
# Manual (see test-16g): slow, so not run automatically on every push.
# ---------------------------------------------------------------------------
build-16g:
stage: build
when: manual
allow_failure: true
timeout: 4h
script:
- echo "Using CC=$CC"
- echo "Using CXX=$CXX"
- test -x "$CC"
- test -x "$CXX"
- source iis-env.sh
- make init
- make dram-build
- make clean all config=$CI_CONFIG_16G DEBUG=0 noc_profiling=0
artifacts:
when: always
expire_in: 2h
paths:
- sim/work/
- sim/bin/cachepool_cluster.vsim
- sim/bin/cachepool_cluster.vsim.gui
- sim/work-dpi/
- software/build/CachePoolTests/
- hardware/deps/dram_rtl_sim/dramsys_lib/DRAMSys/build/lib/
- hardware/deps/dram_rtl_sim/dramsys_lib/DRAMSys/configs/

# ---------------------------------------------------------------------------
# Test stage: run each kernel in parallel on a separate runner.
# Each job downloads the build artifacts, runs one simulation, and checks
Expand Down Expand Up @@ -90,9 +149,69 @@ test:
- python3 util/auto-benchmark/check-ci.py test_${KERNEL}.log
artifacts:
when: always
expire_in: 1 week
expire_in: 3 days
paths:
# Full simulation log
- test_*.log
# Performance-monitor trace files written by the simulator
- sim/bin/logs/

# ---------------------------------------------------------------------------
# Test stage: dual-scalar-per-CC config. Limited to the kernels adapted and
# confirmed working under this config (host0-only Spatz access via
# snrt_cluster_vpu_*/snrt_cluster_is_primary); other tests are not yet
# verified for dual-scalar and are left to the default-config matrix above.
# ---------------------------------------------------------------------------
test-dual:
stage: test
needs: [build-dual]
parallel:
matrix:
- KERNEL:
- fdotp-32b_M32768
- gemv_M512_N128_K32
- fmatmul-32b_M64_N64_K64
- fft-32b_M1024_N16
script:
- mkdir -p sim/bin/logs sim/bin/logs/core sim/bin/logs/noc sim/bin/logs/others
- chmod +x sim/bin/cachepool_cluster.vsim
- BIN="${SW_PREFIX}${KERNEL}"
- sim/bin/cachepool_cluster.vsim software/build/CachePoolTests/$BIN 2>&1 | tee test_dual_${KERNEL}.log
- python3 util/auto-benchmark/check-ci.py test_dual_${KERNEL}.log
artifacts:
when: always
expire_in: 3 days
paths:
- test_dual_*.log
- sim/bin/logs/

# ---------------------------------------------------------------------------
# Test stage: largest available config (16 groups), largest available size
# per kernel. Runs once build-16g (manual) is triggered and succeeds -- see
# build-16g.
# ---------------------------------------------------------------------------
test-16g:
stage: test
needs: [build-16g]
timeout: 4h
parallel:
matrix:
- KERNEL:
- fdotp-32b_M65536
- gemv_M1024_N128_K32
- fmatmul-32b_M128_N128_K128
- fft-32b_M1024_N16
- byte-enable
- multi_producer_single_consumer_double_linked_list_M1_N1350_K10
script:
- mkdir -p sim/bin/logs sim/bin/logs/core sim/bin/logs/noc sim/bin/logs/others
- chmod +x sim/bin/cachepool_cluster.vsim
- BIN="${SW_PREFIX}${KERNEL}"
- sim/bin/cachepool_cluster.vsim software/build/CachePoolTests/$BIN 2>&1 | tee test_16g_${KERNEL}.log
- python3 util/auto-benchmark/check-ci.py test_16g_${KERNEL}.log
artifacts:
when: always
expire_in: 3 days
paths:
- test_16g_*.log
- sim/bin/logs/
2 changes: 1 addition & 1 deletion Bender.lock
Original file line number Diff line number Diff line change
Expand Up @@ -150,7 +150,7 @@ packages:
dependencies:
- tech_cells_generic
spatz:
revision: f6ea19fb26c8bf992ae51a3e4acd3f2a36c6659f
revision: f4741b0a5bcc49103bd8a3db8d51fdf76d240df7
version: null
source:
Git: https://github.com/pulp-platform/spatz.git
Expand Down
3 changes: 3 additions & 0 deletions Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,9 @@ sources:
- hardware/generated/floo_cachepool_noc_pkg.sv
- hardware/src/cachepool_pkg.sv
- hardware/src/cachepool_cc.sv
- hardware/src/cachepool_spatz_lock.sv
- hardware/src/acc_mux.sv
- hardware/src/cachepool_cc_dual.sv
# Barrier
- hardware/src/cachepool_tile_barrier.sv
- hardware/src/cachepool_cluster_barrier.sv
Expand Down
70 changes: 47 additions & 23 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -190,12 +190,12 @@ $(info FLOO_DIR: $(FLOO_DIR))
# Generates the sources for FlooNoC
.PHONY: update-floonoc install-floogen clean-floonoc
install-floogen:
pip install -e $(FLOO_DIR) --quiet
$(PYTHON) -m pip install -e $(FLOO_DIR) --quiet

update-floonoc: $(FLOO_NOC)
$(FLOO_NOC): $(FLOO_CFG)
mkdir -p $(FLOO_GEN_OUTDIR)
PATH="$(HOME)/.local/bin:$(PATH)" floogen pkg -c $(FLOO_CFG) -o $(FLOO_GEN_OUTDIR) --no-format
floogen pkg -c $(FLOO_CFG) -o $(FLOO_GEN_OUTDIR) --no-format

clean-floonoc:
rm -f $(FLOO_NOC)
Expand All @@ -213,7 +213,7 @@ dram-build: $(DRAMSYS_PATH)/README.md dram-config
if [ ! -d "build" ]; then \
mkdir build && cd build; \
$(CMAKE) -DCMAKE_CXX_FLAGS=-fPIC -DCMAKE_C_FLAGS=-fPIC -D DRAMSYS_WITH_DRAMPOWER=ON .. ; \
make -j; \
make -j4; \
fi

$(DRAMSYS_PATH)/README.md: dram-init
Expand Down Expand Up @@ -242,7 +242,7 @@ dram-clean:
fi

dram-init:
make -C ${DRAMSYS_DIR} -j8 dramsys CXX=$(CXX) CC=$(CC)
make -C ${DRAMSYS_DIR} -j4 dramsys CXX=$(CXX) CC=$(CC)

############
# Modelsim #
Expand Down Expand Up @@ -298,6 +298,10 @@ VLOG_DEFS += -DSPATZ_NUM_FPU=$(spatz_num_fpu)
VLOG_DEFS += -DSPATZ_NUM_IPU=$(spatz_num_ipu)
VLOG_DEFS += -DSPATZ_MAX_TRANS=$(spatz_max_trans)
VLOG_DEFS += -DSNITCH_MAX_TRANS=$(snitch_max_trans)
VLOG_DEFS += -DNUM_SCALAR_PER_CC=$(num_scalar_per_core)
ifeq ($(num_scalar_per_core),2)
VLOG_DEFS += -DCACHEPOOL_DUAL_CC
endif
VLOG_DEFS += -DLG_PORT_PER_CORE=$(num_lg_ports_per_core)
VLOG_DEFS += -DRG_PORT_PER_CORE=$(num_rg_ports_per_core)
VLOG_DEFS += -DNOC_PORT_PER_TILE=$(num_noc_ports_per_tile)
Expand Down Expand Up @@ -351,24 +355,28 @@ include sim/sim.mk

TESTS_DIR := $(SOFTWARE_DIR)/tests

# Test-group roots (relative to SOFTWARE_DIR) scanned for data-generated tests.
TEST_ROOTS := cache sync kernels/fp kernels/int rlc tests

# Auto-discover every test that has a script/gen_data.py.
# Convention: script/data_<params>.json → data/data_<params>.h
# Adding a new test or a new data variant needs no Makefile changes:
# - new test: drop gen_data.py + data_<params>.json into its script/ dir
# - new variant: add data_<params>.json to an existing test's script/ dir
DATA_TESTS := $(patsubst $(TESTS_DIR)/%/script/gen_data.py,%, \
$(wildcard $(TESTS_DIR)/*/script/gen_data.py))
DATA_TESTS := $(patsubst $(SOFTWARE_DIR)/%/script/gen_data.py,%, \
$(foreach root,$(TEST_ROOTS), \
$(wildcard $(SOFTWARE_DIR)/$(root)/*/script/gen_data.py)))

define gen_data_rules
$(1)_DATA := $$(patsubst $(TESTS_DIR)/$(1)/script/data_%.json, \
$(TESTS_DIR)/$(1)/data/data_%.h, \
$$(wildcard $(TESTS_DIR)/$(1)/script/data_*.json))
$(1)_DATA := $$(patsubst $(SOFTWARE_DIR)/$(1)/script/data_%.json, \
$(SOFTWARE_DIR)/$(1)/data/data_%.h, \
$$(wildcard $(SOFTWARE_DIR)/$(1)/script/data_*.json))
ALL_GEN_DATA += $$($(1)_DATA)

$(TESTS_DIR)/$(1)/data/data_%.h: \
$(TESTS_DIR)/$(1)/script/data_%.json \
$(TESTS_DIR)/$(1)/script/gen_data.py
$$(PYTHON) $(TESTS_DIR)/$(1)/script/gen_data.py -c $$<
$(SOFTWARE_DIR)/$(1)/data/data_%.h: \
$(SOFTWARE_DIR)/$(1)/script/data_%.json \
$(SOFTWARE_DIR)/$(1)/script/gen_data.py
$$(PYTHON) $(SOFTWARE_DIR)/$(1)/script/gen_data.py -c $$<
endef

$(foreach test,$(DATA_TESTS),$(eval $(call gen_data_rules,$(test))))
Expand All @@ -384,23 +392,32 @@ $(BANDWIDTH_DATA): $(TESTS_DIR)/bandwidth/script/data.json \
.PHONY: gen-data
gen-data: $(ALL_GEN_DATA)

# Clean targets, used to delete generated files
.PHONY: clean.data
clean.data:
rm -f $(ALL_GEN_DATA)

.PHONY: clean.sw
clean.sw:
clean.sw: clean.data
rm -rf ${SOFTWARE_DIR}/build

.PHONY: clean
clean: clean.sw clean.vsim clean.data
.PHONY: clean.generate
clean.generate:
rm -rf $(HJSON_OUT) $(BOOTROM_DIR)/bootdata.cc \
$(BOOTROM_DIR)/bootdata_bootrom.cc \
$(BOOTROM_DIR)/bootrom.sv \
$(BOOTROM_DIR)/bootrom.dump \
$(BOOTROM_DIR)/bootrom.elf \
$(CACHEPOOL_DIR)/wlf* \
$(CACHEPOOL_DIR)/noc_profiling/* \
$(SNRT_BOOTINFO_H)

.PHONY: clean.hw
clean.hw: clean.vsim clean.generate clean-floonoc

.PHONY: clean
clean: clean.hw clean.sw

# Common CMake flags shared by sw and vsim targets.
# vsim appends -DSNITCH_SIMULATOR to point tests at the compiled binary.
SW_CMAKE_FLAGS = \
Expand All @@ -411,7 +428,8 @@ SW_CMAKE_FLAGS = \
-DLLVM_PATH=${LLVM_INSTALL_DIR} \
-DGCC_PATH=${GCC_INSTALL_DIR} \
-DPYTHON=${PYTHON} \
-DBUILD_TESTS=ON
-DBUILD_TESTS=ON \
-DNUM_SCALAR_PER_CORE=$(num_scalar_per_core)

.PHONY: sw
sw: generate bootrom gen-data
Expand All @@ -428,8 +446,11 @@ vsim: generate bootrom dpi ${SIMBIN_DIR}/cachepool_cluster.vsim
############

# Just a shortcut to build everything
.PHONY: hw
hw: generate bootrom vsim

.PHONY: all
all: generate bootrom vsim sw
all: hw sw

########
# Lint #
Expand Down Expand Up @@ -463,9 +484,7 @@ avg-log:
# NoC traffic visualization frontend (fork of https://github.com/ueqri/vis4mesh
# with CachePool-specific fixes/features). Consumes the Vis4Mesh dataset
# directories produced by util/scripts/noc_profiling_to_vis4mesh.py from
# hardware/tb/cachepool_noc_profiling.sv's per-cycle NoC logs. Fetched as a
# plain pinned clone (same pattern as toolchain.mk's riscv-gnu-toolchain/
# llvm-project targets), not a git submodule.
# hardware/tb/cachepool_noc_profiling.sv's per-cycle NoC logs.
NPM ?= npm
VIS4MESH_DIR ?= ${CACHEPOOL_DIR}/util/vis4mesh
VIS4MESH_REPO ?= https://github.com/DiyouS/vis4mesh.git
Expand Down Expand Up @@ -531,13 +550,18 @@ help:
@echo "SW Build:"
@echo ""
@echo "*sw*: build software (generate + bootrom + cmake); overwrites previous build"
@echo "*clean.sw*: remove the software build directory"
@echo "*clean.sw*: remove the software build directory (also runs clean.data)"
@echo ""
@echo "Simulation:"
@echo ""
@echo "*vsim*: build hardware for QuestaSim simulation (use 'sw' to build software separately)"
@echo "*hw*: shortcut for generate + bootrom + vsim"
@echo "*all*: shortcut for hw + sw"
@echo "*clean.vsim*: remove the hardware simulation build [from sim/sim.mk]"
@echo "*clean*: remove SW build, vsim build, and all generated HW files"
@echo "*clean.data*: remove generated data files (gen-data outputs)"
@echo "*clean.generate*: remove generated HJSON/bootrom/wlf/noc_profiling files [from 'generate'/'bootrom']"
@echo "*clean.hw*: clean.vsim + clean.generate"
@echo "*clean*: clean.hw + clean.sw (remove SW build, vsim build, and all generated HW files)"
@echo ""
@echo "Lint:"
@echo ""
Expand Down
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