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GAP9: -O3 hot kernels + hoist L2->L1 tile-control tables to L2 #199

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GAP9: -O3 hot kernels + hoist L2->L1 tile-control tables to L2 #199

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57e7b82
perf(GAP9): -O3 on hot forward kernels (Conv / DWConv / Gemm)
runwangdl Jul 2, 2026
1e91ff7
fix(GAP9): hoist L2->L1 tile-control tables to L2
runwangdl Jul 2, 2026
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13 changes: 12 additions & 1 deletion Deeploy/TilingExtension/CodeTransformationPasses/TilingHoistingMixIn.py
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Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,18 @@ def _hoistValues(self,
else:
cb._type = PointerClass(BasicDataTypes.minimalIntegerType(values))
cb._instance = cb._type(cb.name, ctxt)
cb._memoryLevel = self.memory
# These are constant tile *control* tables (numTiles / DMA cmd / size /
# dims / offsets) read by the (cluster) controller to drive the tiling
# loop and program DMAs -- not bulk tile data. Putting them in the
# innermost tile memory (L1/TCDM) wastes scarce L1 and, on GAP9, places
# them in the contended L1 region next to the cluster master stack: a
# deep stack write can clobber a single table entry, turning a DMA `cmd`
# into a garbage code pointer so mchan_transfer_wait() hangs forever
# (observed on MobileNetV1 training). Keep them in the controller-
# addressable outer memory (L2) instead. Only redirect the L2->L1 pass;
# the L3->L2 pass keeps its tables in L2 (== self.memory), never L3.
# Platforms that don't tile into a level named "L1" are unaffected.
Comment on lines +63 to +73

@Victor-Jung Victor-Jung Jul 8, 2026

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This comment is too verbose and says nothing. You can write a small comment but keep it concise.

cb._memoryLevel = "L2" if self.memory == "L1" else self.memory
return cb

def _hoistReference(self,
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10 changes: 10 additions & 0 deletions TargetLibraries/GAP9/CMakeLists.txt
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Expand Up @@ -31,6 +31,16 @@ target_compile_options(deeploygap9 PRIVATE

target_link_libraries(deeploygap9 PUBLIC pmsis)

# Compile the hot forward kernels at -O3 (set last so it wins over the SDK's
# default -Os). Conv / depthwise-conv / Gemm dominate GAP9 inference cycles;
# -O3 turns on the RISC-V (XpulpV2) hardware loops on their tight inner loops.
Comment on lines +34 to +36

@Victor-Jung Victor-Jung Jul 8, 2026

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Same comment as before, too verbose of a comment.

Also, why only compile these kernels in O3? Why not compile all kernels in O3?

set(_KERNEL_O3_FILES
${CMAKE_CURRENT_LIST_DIR}/../PULPOpen/src/Convolution_fp32.c
${CMAKE_CURRENT_LIST_DIR}/../PULPOpen/src/DWConvolution_fp32.c
${CMAKE_CURRENT_LIST_DIR}/../PULPOpen/src/Gemm.c
)
set_source_files_properties(${_KERNEL_O3_FILES} PROPERTIES COMPILE_OPTIONS "-O3")

#RW: Link PULP-NN
#RW: Set PULP-NN version and bitwidth for pulp-nn-mixed
set(PULPNNVERSION XPULPV2)
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