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x4prosim: X3 panel refresh timing calibrated to the UC8253 device - #5
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Decode SPI_CLOCK for every CPU transaction and hold CMD.USR until a virtual clock timer expires. Transfer the latched bytes to the SSI slaves at expiry, then clear USR and raise TRANS_DONE so polling firmware observes bus time. Expose a transaction-overhead-us property with a zero default and trace the selected clock, byte count and duration. Ignore duplicate starts while busy and cancel pending transfers on reset. Both system targets build; X4 Pro qtest checks clock dividers, setup overhead, pending USR and UPDATE writes, and the completion interrupt boundary. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01T57W7AZf7tgmkuDMMSaWwz
Hold read tokens and write readiness until virtual-clock deadlines instead of making each block immediately available. Track completed read and write sectors separately to select sequential first-block access and random first-write busy time, including CMD18 inter-block delays and CMD25 stop-token busy time. Expose six uint32 microsecond properties with zero generic defaults, and apply the provisional X3 timings without overriding explicit -global settings. Preserve the existing R1 idle, immediate write-token dispatch and CMD13 SPI R2 behavior; retain timed adapter state in an optional migration subsection. Trace latency decisions and document the properties, calibration limits and command-line overrides. Both targets build without warnings in changed files; isolated adapter tests cover exact SDSC/SDHC deadlines and zero defaults, and QMP checks the X3 properties and explicit overrides. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01T57W7AZf7tgmkuDMMSaWwz
The X3 defaults for the GPSPI setup costs and the ssi-sd card latencies now come from a 3-boot probe on a real X3 (40 MHz SCLK, SdFat SHARED mode, read/write x sequential/random/repeated x 1..32 sectors). All 30 median totals match the device: reads within 3 %, writes within 13 %. The probe's device table, the comparison script and the notes live in x4prosim/sdcal/; the raw emulator log stays with the session evidence. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01T57W7AZf7tgmkuDMMSaWwz
Decode both state repeats and the outer group repeat for UC8279d, count VCOM alongside transition rows, and retain UC8253 six-byte groups. Add refresh overhead and power timing properties with microsecond deadlines and per-row refresh tracing. Document the provisional PLL revision mapping and equal-row calibration limitation. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01T57W7AZf7tgmkuDMMSaWwz
Select the measured UC8253 variant on X3 while preserving the UC8279d selector and explicit timing overrides. Fit all measured refresh banks with a 12850 us frame period and 138000 us fixed overhead, set PON to 127 ms, and retain unmeasured POF at 2 ms. Include the fit, raw emulator waits and per-row trace, Home screenshot, reproduction steps, and remaining hardware uncertainties. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01T57W7AZf7tgmkuDMMSaWwz
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Stacked on the SD card timing branch (the three SD commits are the base; only the two panel commits are new here).
The X3 machine's panel refreshes finished in the LUT's frame count times a fixed 20 ms, and power-on took 2 ms. Measured on a real X3 the device's firmware log shows 381 ms for a page turn, 485 ms for the black-and-white pass that precedes a grayscale pass, 228 ms for the grayscale pass, 935 ms for a full refresh and 127 ms for power-on; the emulator gave 380 / 540 / 140 / 1240 / 2. Two things were wrong: the machine presented itself as the UC8279d run of the X3 while this device is the UC8253 run (its VER probe answers nothing), so the firmware ran a different driver with different waveforms, and the timing rule was missing a fixed cost.
Model
hw/display/uc8279.c: BUSY after DRF isrefresh-overhead-us + frames x frame-us, frames being the longest of the VCOM and four transition LUT rows with repeats applied (both the 6-byte UC8253 and the 7-byte UC8279d group formats are decoded; the latter's state repeats were previously ignored). PLL (0x30) scales the frame period relative to the driver's reference code.pon-ms/pof-msreplace the fixed 2 ms. A trace event prints the five row totals, the PLL code and the resulting BUSY.hw/riscv/esp32c3.c:-machine x3now defaults to the UC8253 variant (-global uc8279.uc8253=falseselects the UC8279d) with the calibrated values: 138 ms overhead, 12.85 ms per frame at PLL 0x09, power-on 127 ms.Calibration
A probe build of CrossPoint printed, for every refresh, the waveform bank, its LUT frame totals and the BUSY time, on the device and on the emulator. One affine law fits every bank the firmware uses:
Notes with the fit, the LUT decoding rules and what is still inferred (the PLL rate tables come from the UC8179c and UC8253c documents, not a sweep on this panel):
x4prosim/sdcal/panel.md.Effect on a reading workload
CrossPoint's
Page render (tiled)stages, median of 6 page turns, ms. Same firmware, card contents, settings and pages on every side.Cold-open first renders: Aesop 3356 ms vs 3575 on the device, Demian 3338 vs 3486. The remaining gap is CPU-bound work (grayscale rendering 60 vs 88–108 ms,
bw_render13 vs 35 ms) under-icount shift=2; a 52 KB plane write is 47 ms here against 51 ms on the device for the same reason.Limits
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https://claude.ai/code/session_01T57W7AZf7tgmkuDMMSaWwz