Skip to content
View pravin2007-ctrl's full-sized avatar

Block or report pravin2007-ctrl

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
pravin2007-ctrl/README.md

πŸ‘‹ Hi, I'm PRAVIN A

He/Him
πŸŽ“ B.E. Electronics and Communication Engineering @ Sri Eshwar College of Engineering
πŸ’Ό FOSSEE Intern @ IIT Bombay (Remote)
πŸ“ Namakkal, Tamil Nadu, India


πŸš€ About Me

Aspiring Semiconductor and VLSI Engineer passionate about Digital IC Design, Circuit Simulation, and RTL Development using Verilog.
I explore everything from device physics and circuit analysis to FPGA prototyping and EDA tools.

πŸ’‘ My goal is to contribute to innovations in semiconductor and next-generation chip technologies.


🧠 Current Role

FOSSEE, IIT Bombay (Remote Internship)
Research Migration Contributor | Analog Circuit Design
πŸ—“οΈ Oct 2025 – Present

Key Contributions:

  • Migrated & simulated analog signal circuits (CMOS-based charge pumps) using KiCad & Ngspice.
  • Completed projects:
    • πŸ”Έ DC–DC Voltage Multiplier (Dickson Charge Pump)
    • πŸ”Έ Low-Voltage Cross-Coupled Charge Pump
    • πŸ”Έ Six-Stage Linear CMOS Charge Pump
  • Enhanced expertise in analog system modeling and low-voltage CMOS circuit design.

πŸŽ“ Education

πŸŽ“ B.E - Electronics and Communication Engineering
πŸ“ Sri Eshwar College of Engineering, Coimbatore (2024 – 2028)

🏫 Higher Secondary (Mathematics & Computer Science)
πŸ“ Holy Angel’s Matric Higher Secondary School (2023 – 2024) – Scored 95%


πŸ’Ό Projects & Research Contributions

πŸ”Ή Electronic Voting System (Xilinx Vivado)

  • Designed during a VLSI Hackathon.
  • Developed Verilog-based real-time voting system with GitHub version control.

πŸ”Ή Analog Design using Cadence Virtuoso

  • Designed Common Emitter Amplifier.
  • Performed DC & transient analysis to validate transistor biasing and gain.

πŸ”Ή Adaptive Vision (IoT + AI Project)

  • Built smart lighting control system with motion & rain sensors.
  • πŸ† Won Special Prize at SelfE Hackathon 2024.

πŸ”Ή Research Migration Projects (FOSSEE – IIT Bombay)

  • Simulated & migrated CMOS charge pump circuits using open-source EDA tools.
  • Contributions published under NMEICT – eSim Repository.

🧾 Certifications

Organization Certification Date
FOSSEE, IIT Bombay Research Migration Project – Dickson Charge Pump Oct 2025
FOSSEE, IIT Bombay Low-Voltage Cross-Coupled Charge Pump Oct 2025
FOSSEE, IIT Bombay Six-Stage CMOS Charge Pump Oct 2025
Udemy Python Programming Masterclass Jul 2025
Udemy Mastering DSA using C/C++ May 2025
Scaler C++ Certificate of Excellence Feb 2025
Spoken Tutorial, IIT Bombay C Programming Dec 2024
Sololearn Introduction to C Dec 2024
Hack2Skill Google Solution Challenge Certificate Mar 2025
Bharathidasan University Office Automation (Distinction) 2018

🧩 Skills

🧠 Technical

7 minutes ago

Revise README with badges and formatting updates

VLSI Cadence Virtuoso Xilinx Vivado eSim Ngspice LTSpice

πŸ’» Programming

C C++ Python Verilog

βš™οΈ Tools

Arduino IDE FPGA GitHub Proteus

10 minutes ago

Revise README with personal and project details

πŸ’¬ Soft Skills

7 minutes ago

Revise README with badges and formatting updates

  • 🀝 Team Collaboration
  • 🧩 Problem Solving & Debugging
  • πŸ“˜ Technical Documentation
  • πŸ” Research & Analytical Thinking
    10 minutes ago

Revise README with personal and project details


πŸ… Achievements & Highlights

  • πŸŽ“ FOSSEE Internship @ IIT Bombay (eSim Initiative) – 2025
  • πŸ† Special Prize – SelfE Hackathon 2024
  • πŸ’» Top 3rd Performer – Skillrack Platform (2024–2025)
  • βš™οΈ Simulathon 2025 Participant (Proteus Simulation)
  • 🌍 Finalist – Google Developer Group Solution Challenge 2025
  • πŸ₯‰ Freshwarite 2024 – 3rd Position
  • πŸ”₯ CodeChef Gold Streak Badge (50-day streak)

7 minutes ago

Revise README with badges and formatting updates

🧠 Workshops & Events

🎯 Analog Design using Cadence (SiCrest Semiconductors) – 2025
πŸ’‘ Catalyst’25 – CMOS Logic Design Workshop (Sri Eshwar College)
πŸ“˜ IEEE Xplore Research Session (EBSCO) – Research tools training
πŸ€– Machine Learning & Data Science Workshop (KIRIT’s) – 2024
10 minutes ago

Revise README with personal and project details


6 minutes ago

Revise README with badges and formatting updates

🌐 Portfolio & Contact

GitHub

Pinned Loading

  1. FOSSEE_eSim_circuit_repo FOSSEE_eSim_circuit_repo Public

    1

  2. Health_Dial Health_Dial Public

    JavaScript 1

  3. pravin pravin Public

  4. tourismWebPage tourismWebPage Public

    HTML 1

  5. ROOBAK-S/DIGITAL_VOTING_SYSTEM ROOBAK-S/DIGITAL_VOTING_SYSTEM Public

    Verilog