[6.18] Rebase ARM commits from 4.14 kernel - #286
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In preparation for upgrading to gcc 4.7 we need a copy of the pre-generated header arm-nilrt-linux-gnueabi-elfconfig.h that matches the toolchain prefix. This file is identical to: arm-none-linux-gnueabi-elfconfig.h Signed-off-by: Gratian Crisan <gratian.crisan@ni.com> Acked-by: Brad Mouring <brad.mouring@ni.com>
In order to support building the tools needed for on-target versioning for x86_64 targets (since HOSTCC continues to be x86), adding a pregenerated header for that toolchain. Signed-off-by: Brad Mouring <brad.mouring@ni.com> Acked-by: Gratian Crisan <gratian.crisan@ni.com>
Signed-off-by: Ben Shelton <ben.shelton@ni.com> Acked-by: Scot Salmon <scot.salmon@ni.com> Acked-by: Terry Wilcox <terry.wilcox@ni.com> Natinst-ReviewBoard-ID: 69848 [gratian: convert to new syscall table format for arm] Signed-off-by: Gratian Crisan <gratian.crisan@ni.com> [cvadrevu: Updated to just add missing Zynq code] Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
On systems where FPGA autoload is controlled by software, we need a way to determine if a system has just had power applied. This is necessary to implement the autoload on every power-on feature. Once the FPGA has been autloaded after power-on, software sets a bit in the CPLD so that subsequent (non power-on) resets don't cause the FPGA to be autoloaded again. The CPLD provides the HARD_BOOT_N bit for this purpose. On systems where FPGA autoload is controlled by hardware, such as Smasher, we need to set this bit at some point after power-on so that software can correctly determine the reset state of the controller. Since software has no insight into the status of FPGA autoload on these systems, we can just set this bit if necessary when the driver loads. Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com> [cvadrevu: Fixed trivial conflicts with 91d93a7 ("nirtfeatures: Only register bi-color LEDs on supported targets")] 6c83dd7 ("nirtfeatures: Added NI RT features driver")] Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
The BIOS will set the HARD_BOOT_N bit at post, so the driver no longer needs to do this. Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com> [cvadrevu: Fixed trivial conflicts with 91d93a7: ("nirtfeatures: Only register bi-color LEDs on supported targets") f3ab444: ("nirtfeatures: Use managed resource allocation")] Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
Add the leds-ni793x driver which controls the RT User 1 LED on the NI-793xR devices. The RT User 1 LED control is exposed through the Zynq FPGA logic. Signed-off-by: Francesca Ramadori <francesca.ramadori@ni.com> Signed-off-by: Brad Mouring <brad.mouring@ni.com> Acked-by: Josh Cartwright <joshc@ni.com> Acked-by: Ben Shelton <ben.shelton@ni.com> [cvadrevu: Fixed trivial conflicts due to newer modules] [cvadrevu: Updated ni793x_leds_remove signature for newer kernel] [cvadrevu: Replaced ni793x_leds_ids with ni793x_led_ids] Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com> leds-ni793x: Fix build for newer kernel
Add documentation for leds-ni793x devicetree bindings. This driver controls the RT User1 LED on the FlexRIO NI-793xR devices. Signed-off-by: Francesca Ramadori <francesca.ramadori@ni.com> Signed-off-by: Brad Mouring <brad.mouring@ni.com> Acked-by: Josh Cartwright <joshc@ni.com> Acked-by: Ben Shelton <ben.shelton@ni.com>
Clients are drivers for peripherals with physical lines routed through the FPGA. Ethernet and serial will want to receive notifications so they can avoid accessing hardware while the FPGA is unprogrammed. Signed-off-by: Kyle Teske <kyle.teske@ni.com> Natinst-ReviewBoard-ID: 26536 [cvadrevu: Fixed trivial conflicts due to newer modules] Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
We add a separate notification which will get called when FPGA programming fails. This is to enable client drivers to know when to stop waiting for FPGA to come up, if the re-programming fails. Signed-off-by: Karthik Manamcheri <karthik.manamcheri@ni.com>
If fpgaperipheral_probe succeeds, it generates no debug output, even at the highest loglevel. Add a success message to make device tree debugging easier. Signed-off-by: Ben Shelton <ben.shelton@ni.com>
This is a snapshot of the Xilinx-provided PL353 NAND driver as of commit 3fa059c ("nand: pl353: Renamed zynq_nand driver as pl353_nand"). The original driver author is Punnaiah Choudary Kalluri <punnaia@xilinx.com>. Signed-off-by: Josh Cartwright <joshc@ni.com> [cvadrevu: Fixed trivial conflicts due to newer modules] Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
The default 3.10 NAND driver does not support subpage reads or writes for our device, which causes it not to play nicely with partitions that have already been formatted with this support. This commit forward-ports the following commits to enable this feature: - NAND: Added subpage read support for on-die ECC devices using Xilinx PS NAND controller. - Zynq NAND: Fixed block erase timeout problem and off-by-one math error - Zynq NAND: Subpage write support. Acked-by: Jeff Westfahl <jeff.westfahl@ni.com> Signed-off-by: Ben Shelton <ben.shelton@ni.com>
Replace the NAND READ0 command with an RNDOUT command if the READ0 is for the most recently read page and no other command has been sent to the NAND that would make another READ0 necessary. Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com>
When using on-die ECC, check the NAND status after READ0 operations for an ECC warning or error. Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com>
In some cases, CS remains asserted to the NAND chip after an operation has completed. We should make sure to deassert CS when the chip is no longer in use. Refactored to avoid variable hiding. Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com>
The Zynq static memory controller is based on ARM PL353. The following commit [3fa059c nand: pl353: Renamed zynq_nand driver as pl353_nand] renamed the driver to "pl353-nand" to match the hardware. This creates problems on shipping hardware due to a mismatch between what u-boot expects (via bootargs/mtdparts) and the kernel driver name. This commit reverts the NAND driver name to the old "xilinx_nand" in order to preserve compatibility. Signed-off-by: Gratian Crisan <gratian.crisan@ni.com> Acked-by: Joseph Hershberger <joseph.hershberger@ni.com> Acked-by: Terry Wilcox <terry.wilcox@ni.com> Natinst-ReviewBoard-ID: 79256
In ed4f85c (mtd: nand: embed an mtd_info structure into nand_chip), an mtd_info structure was embedded into the nand_chip struct since all drivers were doing the same thing. This was an attempt to simplify and streamline. In 862eba5 (mtd: nand: make use of mtd_to_nand() in NAND core code) this change was put into practice, changing the nand_core's mapping of mtd-to-nand to use the embedded mtd_info in the nand_chip struct. Update the pl353_nand driver to use this new embedded structure. Signed-off-by: Brad Mouring <brad.mouring@ni.com>
Add `enable_subpage_read` and `enable_subpage_write` load-time options to toggle subpage read/write operations on pl353 chips. Both options are enabled by default, and may be toggled in the boot loader. Signed-off-by: Haris Okanovic <haris.okanovic@ni.com> Acked-by: Gratian Crisan <gratian.crisan@ni.com> Acked-by: Jeff Westfahl <jeff.westfahl@ni.com> Natinst-CAR-ID: 599280 Natinst-ReviewBoard-ID: 151758 (cherry picked from commit 311a5711cfdbfa20e3f4ec2dbd429f96b9f76c2f)
Add dsb(st) [1] after writes to command register to ensure the chip receives them before ndelay()-ing to synchronize driver/chip state. The subsequent ndelay()s (after dsb(st)) gives the chip enough time to process "quick" commands (like RNDOUT) which don't change status flags or issue interrupts upon completion. They are assumed to complete at most 100ns after delivery on the bus. It's therefore critical to ensure they make it all the way down to the chip before the driver ndelay()s for on-chip processing. Otherwise, commands may get buffered in the interconnect between the CPU and chip while the driver waits. Subsequent read/write operations may then be delivered inside the on-chip processing window resulting in incorrect behavior. In particular, a READ0 (page select + col change), followed by RNDOUT (column change only), followed by data reads <1page in size results in sporadic one-byte data corruption, particularity when the bus is busy. Testing: No longer see a sporadic 1 byte corruption after RNDOUT by repeatedly reading the entire Linux file system after fs-cache drop for 48 hours. Verified RNDOUT requires the ndelay() by unsuccessfully attempting to remove it for that command. Doing so results in the same sporadic 1 byte corruption in the aforementioned read test. Ran fio [2] with random read/write+verify for 48 hours; no corruptions reported. Config: rw=randrw, size=100M, bs=5k, verify=sha256, numjobs=5 Hardware: National Instruments cRIO-9068 [3] Xilinx Zynq-7020 SoC MT29F8G08ADBDAH4 8GB NAND [1] http://infocenter.arm.com/help/topic/com.arm.doc.dui0489c/CIHGHHIE.html#id4692433 [2] http://linux.die.net/man/1/fio [3] https://sine.ni.com/nips/cds/view/p/lang/en/nid/211620 Signed-off-by: Haris Okanovic <haris.okanovic@ni.com> Signed-off-by: Brad Mouring <brad.mouring@ni.com> Acked-by: Jeff Westfahl <jeff.westfahl@ni.com> Natinst-CAR-ID: 599280 Natinst-ReviewBoard-ID: 152950
Haven't yet figured out why this is required...hack it. Signed-off-by: Josh Cartwright <joshc@ni.com>
Commit aab616e ("mtd: kill the nand_ecclayout struct") removed the nand_ecclayout struct. Convert the pl353_nand driver to the new mtd_ooblayout_ops model. Fixes: 627a2ef8fb01 ("mtd: nand: pl353: add snapshot of driver from linux-xlnx tree") Signed-off-by: Gratian Crisan <gratian.crisan@ni.com>
Commit 7f2b092 ("mtd: nand: kill the ecc->layout field") removed direct access to the ecc layout field. Use instead the mtd_ooblayout_xxx() helper functions in places where the eccpos[] array was accessed directly. Fixes: 627a2ef8fb01 ("mtd: nand: pl353: add snapshot of driver from linux-xlnx tree") Signed-off-by: Gratian Crisan <gratian.crisan@ni.com>
The NI Zynq prototype board has a CPLD that provides various board-management capabilities. Signed-off-by: Josh Cartwright <josh.cartwright@ni.com> Signed-off-by: Jaeden Amero <jaeden.amero@ni.com> Acked-by: Jeff Westfahl <jeff.westfahl@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> [cvadrevu: Fixed trivial conflicts due to newer module] Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
This provides a general purpose, raw interface to the CPLD's scratchpad. The scratchpad can be used to communicate between soft reboots of the target. Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
This is a read/write attribute that will set the necessary bits in the scratch registers used to determine which mode the board boots into. Currently, valid modes are 'runtime', 'safemode', and 'recovery'. Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
Signed-off-by: Josh Cartwright <josh.cartwright@ni.com> Signed-off-by: Scot Salmon <scot.salmon@ni.com> Acked-by: Brad Mouring <brad.mouring@ni.com> Acked-by: Josh Cartwright <josh.cartwright@ni.com> Natinst-ReviewBoard-ID: 36482
Use the SLCR to reboot the zynq if a reset function is not provided. Signed-off-by: Josh Cartwright <josh.cartwright@ni.com> Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com> Acked-by: Jeff Westfahl <jeff.westfahl@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Natinst-ReviewBoard-ID: 90458
This will expose the switches as sysfs attributes for consumption by the RT utilities VIs. Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
Add support for the Dos Equis CPLD watchdog, implementing the NI Watchdog ioctl interface with a misc device. Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com> Signed-off-by: Scot Salmon <scot.salmon@ni.com> Acked-by: Brad Mouring <brad.mouring@ni.com> Acked-by: Josh Cartwright <josh.cartwright@ni.com> Natinst-ReviewBoard-ID: 36482
Signed-off-by: Ioan Cornea <ioan.cornea@ni.com>
NI software shipped with an early implementation of the device_poll interface with differences from the current implementation. This commit provides a compatibility layer that allows this NI software to function. This is an internal patch that should never be submitted for inclusion upstream. Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com> Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com> Reviewed-by: Jaeden Amero <jaeden.amero@ni.com> Natinst-ReviewBoard-ID: 108252
Add support for taking Ethernet down and up when the FPGA is reloaded. Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com> Acked-by: Jaeden Amero <jaeden.amero@ni.com> Acked-by: Ben Shelton <ben.shelton@ni.com> Natinst-ReviewBoard-ID: 84654 Natinst-ReviewBoard-ID: 99911 Natinst-CAR-ID: 528734 Natinst-CAR-ID: 527188 (joshc: minor checkpatch cleanups) Signed-off-by: Josh Cartwright <joshc@ni.com> [cvadrevu: Fixed trivial merge conflicts] [cvadrevu: Make macb_fpga_notifier static to avoid build warning] Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com> macb_main: Add declaration for macb_fpga_notifier. TODO: fixup original commit later
Since hardware checksumming is not supported, reset the TXCOEN bit in DMACFG. If unitialized, this bit causes checksum offloading to be left on in hardware, with software thinking it is off, and for a checksum offloading bug in hardware to cause small UDP packets (<= 2 bytes) to be sent with an incorrect checksum (0xffff). We can't fix this problem by zeroing the checksum field in outgoing UDPv4 packets as implemented by Jeff Westfahl or Xilinx in their xemacps driver because it breaks packet forwarding (where it is illegal to modify the checksum of forwarded packets with unknown validity). We don't yet know a way to fix this problem other than to not use hardware checksum offloading. This commit will need to be reworked before it is upstreamable. We just need a fix in the LabVIEW RT Linux kernel right now for release. Ideally, we'd continue to work with upstream to solve the problem, but this is an emergency and we need to test and ship right away. Signed-off-by: Mihai Neagu <mihai.neagu@ni.com> Signed-off-by: Jaeden Amero <jaeden.amero@ni.com> Reviewed-by: Ben Shelton <ben.shelton@ni.com> Reviewed-by: Josh Cartwright <joshc@ni.com> Natinst-CAR-ID: 516373 Natinst-ReviewBoard-ID: 97988 (joshc: also hack up hw_features to never advertise hw csum support) Signed-off-by: Josh Cartwright <joshc@ni.com>
Even when the PHY is stopped by macb_close, it still hangs on to its irq. Explicitly call phy_stop_interrupts to make sure the interrupt line is ignored while the FPGA is reloading to avoid interrupt storms from floating lines. Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com> Reviewed-by: Ben Shelton <ben.shelton@ni.com> Reviewed-by: Jaeden Amero <jaeden.amero@ni.com> Natinst-ReviewBoard-ID: 98279
This function stops the PHY state machine, but without running the machine. Ever since 7ad813f, phy_stop_machine runs it and brings the link down, which isn't always what you want. Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com> Signed-off-by: Brad Mouring <brad.mouring@ni.com> Acked-by: James Minor <james.minor@ni.com> Natinst-ReviewBoard-ID: 214996 [cvadrevu: Fixed trivial conflicts with 59088b5: ("net: phy: avoid kernel warning dump when stopping an errored PHY") a3320bc: ("net: phy: make phy_trigger_machine static")] Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
Use this new function to avoid bringing the link down when an FPGA bitfile is loaded. This minimizes the time spent with no network afterwards. Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com> Signed-off-by: Brad Mouring <brad.mouring@ni.com> Acked-by: James Minor <james.minor@ni.com> Natinst-ReviewBoard-ID: 214996
In order to synchronize macb_stop and macb_start_xmit, turn all the tx queues off before going down and back on again before going up during FPGA reloads. Not synchronizing these functions would result in a crash during the reload if frames are transmitted. Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com> Signed-off-by: Brad Mouring <brad.mouring@ni.com> Acked-by: Zach Brown <zach.brown@ni.com> Acked-by: James Minor <james.minor@ni.com> Natinst-ReviewBoard-ID: 218609 Natinst-CAR-ID: 672398
NI uses a module from LSR that does not have calibration constants for channel 14. As such, channel 14 should never be used. This change is to retain parity with NI's shipped 3.2 kernel for purposes of compliance, so it should not be upstreamed. Signed-off-by: James Minor <james.minor@ni.com>
In order to prevent us from sending out anything on channels that are illegal in some countries, we wait until we see beacons from the AP before trying to connect on those channels. This change is to retain parity with NI's shipped 3.2 kernel for purposes of compliance, so it should not be upstreamed. Signed-off-by: Tim Ousley <tim.ousley@ni.com> [reworked for 3.14 branch and for coding style ] Signed-off-by: James Minor <james.minor@ni.com>
Commit 57fbcce ("cfg80211: remove enum ieee80211_band") upstream removed the ieee80211_band enum in favour of using the nl80211_band enum directly. Convert the TI wl12xx driver's use of ieee80211_band to nl80211_band enum. Fixes: ce3a405b2e61 ("wl12xx: Disallow channels above 11 until beacons are seen") Signed-off-by: Gratian Crisan <gratian.crisan@ni.com>
The SD spec version 6.0 section 6.4.1.5 requires that Vdd must be lowered to less than 0.5V for a minimum of 1 ms when powering off a card. Increase our wait to 15 ms so that voltage has time to drain down to 0.5V. Signed-off-by: Kyle Roeschley <kyle.roeschley@ni.com> Signed-off-by: Brad Mouring <brad.mouring@ni.com> Acked-by: James Minor <james.minor@ni.com> Acked-by: Brandon Streiff <brandon.streiff@ni.com> Natinst-ReviewBoard-ID: 203804
Per the SD Host Controller Simplified Specification v4.20 §3.2.3, change the SD card clock parameters only after first disabling the external card clock. Doing this fixes a spurious clock pulse on Baytrail and Apollo Lake SD controllers which otherwise breaks voltage switching with a specific Swissbit SD card. Signed-off-by: Kyle Roeschley <kyle.roeschley@ni.com> Signed-off-by: Brad Mouring <brad.mouring@ni.com> Acked-by: Tony Liechty <tony.liechty@ni.com> Acked-by: Nathan Sullivan <nathan.sullivan@ni.com> Natinst-ReviewBoard-ID: 236135 Natinst-CAR-ID: 694815
Some SD controllers require a delay between clearing SDHCI_CLOCK_CARD_EN and changing the SD clock dividers in order to avoid a runt clock pulse which can otherwise cause problems with some SD cards. Signed-off-by: Kyle Roeschley <kyle.roeschley@ni.com> Signed-off-by: Brad Mouring <brad.mouring@ni.com> Acked-by: Tony Liechty <tony.liechty@ni.com> Acked-by: Nathan Sullivan <nathan.sullivan@ni.com> Natinst-ReviewBoard-ID: 236135 [cvadrevu: Fixed trivial conflicts due to new quirks] Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
On some SD host controllers, we can see two SD card insert interrupts when inserting a card. This causes mmc_rescan() to be called twice in quick succession and generate one or two SD card clock pulses, which can cause some SD cards to become unresponsive. Signed-off-by: Kyle Roeschley <kyle.roeschley@ni.com> Signed-off-by: Brad Mouring <brad.mouring@ni.com> Acked-by: Tony Liechty <tony.liechty@ni.com> Acked-by: Nathan Sullivan <nathan.sullivan@ni.com> Natinst-ReviewBoard-ID: 236135 [gratian: fix conflict with fec7967 ("mmc: sdhci: Factor out sdhci_enable_clk")] Signed-off-by: Gratian Crisan <gratian.crisan@ni.com> [cvadrevu: Fixed trivial conflicts due to new quirks] Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
With the Baytrail SD controllers on cRIO-905x, we can run into two conditions which cause functional problems with the NI-recommended microSD card. The first is a runt pulse after SD card clock disable, which is fixed by using SDHCI_QUIRK2_NEED_DELAY_AFTER_CLK_DISABLE to wait after disabling the clock. The second is receiving two SDHCI_INT_CARD_INSERT interrupts, which causes us to set up the card twice a make our recommended microSD card unresponsive. Work around this by using SDHCI_QUIRK2_SPURIOUS_CARD_INSERT_INTERRUPT. Signed-off-by: Kyle Roeschley <kyle.roeschley@ni.com> Signed-off-by: Brad Mouring <brad.mouring@ni.com> Acked-by: Tony Liechty <tony.liechty@ni.com> Acked-by: Nathan Sullivan <nathan.sullivan@ni.com> Natinst-ReviewBoard-ID: 236135 Natinst-CAR-ID: 696865 Natinst-CAR-ID: 694815
By default, the interrupt output of the Marvell 88E1512 PHY is configured as an LED output, and is driven low. If we have a case where eth1 is brought up before eth0, this causes an interrupt storm, and Linux eventually gives up and disables the PHY interrupt line. Adding a probe function to the Marvell 88E1512 PHY driver and moving the interrupt output configuration there resolves this problem. [bm: Adjust for d2fa47d 'phy: marvell: Add ethtool statistics counters'] Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com> Signed-off-by: Mihaly Varga <mihaly.varga@ni.com> Acked-by: Brad Mouring <brad.mouring@ni.com> Acked-by: Ben Shelton <ben.shelton@ni.com> Acked-by: Jaeden Amero <jaeden.amero@ni.com> Natinst-ReviewBoard-ID: 81627 [bm: Restore correct page on LED/irq config] Signed-off-by: Brad Mouring <brad.mouring@ni.com> Acked-by: Jeff Westfahl <jeff.westfahl@ni.com> Natinst-ReviewBoard-ID: 148255 [gratian: split LED pin setup from m88e151x_probe; fixes conflict with 0b04680 ("phy: marvell: Add support for temperature sensor")] Signed-off-by: Gratian Crisan <gratian.crisan@ni.com> [cvadrevu: Fixed trivial conflict with b697d9d ("net: phy: marvell: add SFP support for 88E1510")] [cvadrevu: Updated marvell_get_page to marvell_read_page due to 424ca4c ("net: phy: marvell: fix paged access races")] Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
Upstream removed spin lock usage in the set_ios path with commit d1e4f74 ("mmc: sdhci: Do not use spin lock in set_ios paths"), which means that our calls to spin_(un)lock_irq() in sdhci_set_clock() now cause an error on boot if a card is not present or a crash if one is present. Remove these calls so we don't do that and to match upstream's change. Fixes: 815777e ("mmc: sdhci: Add quirk for delay between clock disable and param change") Fixes: 30d2f45 ("mmc: sdhci: Add quirk work around double rescan") Signed-off-by: Kyle Roeschley <kyle.roeschley@ni.com> Acked-by: Gratian Crisan <gratian.crisan@ni.com> Acked-by: Brandon Streiff <brandon.streiff@ni.com> Natinst-ReviewBoard-ID: 264712 Natinst-CAR-ID: 720310
NI roboRIO 2.0 has relocated the clock pin from 1.8V bank to 3.3V bank. Hence, it required to update both product and supported version to indicate the changes in HW. Signed-off-by: Kim Khiam Lim <kim.khiam.lim@ni.com>
Import the NI Zynq board device trees from the 4.14 kernel and add them to the Xilinx DTB build list. Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
These have been superceded by ni-<devicecode>.dts. Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
The NI device trees were copied from the 4.14 kernel and still reopen SoC nodes using their old names and hierarchy. The current Zynq device tree defines these nodes with labels and uses gpio0 for the GPIO controller. Convert the NI board files to extend the existing amba, I2C, SPI, and ADC nodes through label references. Update GPIO references from gpio to gpio0 and move the myRIO I2C and SPI configuration to the corresponding labeled nodes. This allows the NI Zynq device trees to compile against the current zynq-7000.dtsi. Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
Set the address and size cells on the NAND controller so the nand@0 reg property is parsed correctly. Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
The CoreSight blocks are not accessible on NI Zynq targets. Reading their AMBA identification registers hangs the SoC before any driver binds. Disable the nodes to allow the system to boot. Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
phy_start_interrupts, phy_stop_interrupts have been removed in newer kernel. Replace them with phy_request_interrupt, phy_free_interrupt. Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
Drop the unused device ID argument from probe and change remove to return void, matching the current I2C driver callback signatures. Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
UPF_IOREMAP defers mapping the register resource until the serial port is started. The NI 16550 driver accesses registers during probe to determine FIFO sizes and configure the PMR, before the port has been started. Map the MMIO resource with devm_ioremap() during probe and assign the result to port->membase so these early register accesses use a valid mapping. Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
Port remaining defconfig changes from 4.14 kernel. Refresh it against Linux 6.18 while retaining the features required by NI Zynq targets. Enable PREEMPT_RT, RCU callback offloading, NI platform drivers, and the networking, USB, storage, filesystem options, etc. Regenerate the defconfig to account for current symbols and dependencies. Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
Ported from 4.14 and updated to work on 6.18 kernel. Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
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Rebase ARM commits from 4.14 kernel.
Majority of commits had merge conflicts or needed updates to be able to build on 6.18 kernel. I've recorded details in commit messages itself.
There are some commits I haven't cherry-picked either due to merge conflicts that required more detailed analysis or due to them failing build. I will update here details of those and work items.
Testing
ni-pkgtargetIssues