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Verilator don't support `highz` strengh, and I suppose `weak` has equivalent ordering compare to the order strengths used?
Verilator don't support program decls inside a module. This may change the timing of things and cause data races? Not sure how much of a program is this.
Verilator does not support `disable <label>` when `disable` ins't in the scope of `<label>`. Fix it by replacing its uses with a explict bit signal, that is checked by the loop to know if it must exit.
Verilator doesn't support unclocked assertions. I suppose I could also have fixed this by make all assertions sequential, like `assert #0`? Not sure, but I don't need the assertions (for now).
Trying to debug it, the problem came from waiting on delays. The problem is that verilator is design to work on a cycle by cyle basis, and this project uses a lots of delays.
Actually, I think removing all delays make the entire thing don't work anymore. Appear to became stuck on DMA or something? Not sure, appears to not even exit quickboot.
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Need to make a bunch of changes because Verilator does not support some features of SystemVerilog.
When I got this running, the simulation was about 100x slower than
vvp. Looking at the logs, Verilator appears to be spending a lot of work waiting for delays.Knowing that Verilator was designed to handle purely cycle-based designs, I guess that the extensive use of delays throughout the project was hitting a pathological case. So I removed all delays.
But when I finally got it to run far enough, the simulation was not working. I guess maybe removing all timings broke it, but could very well have other problems.
I am publishing my work here in case anyone else also wanted to pursue this.