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[RFC]: # "Integration of sparse-ternary-fma for accelerated ternary operations" #365
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- Add sparse-ternary-fma library as 3rdparty dependency - Create adapter layer (ggml-bitnet-stfma.h/cpp) for BitNet integration - Implement encoding conversion between BitNet and STFMA formats - Implement int32 variants of sparse ternary FMA with AVX2/AVX-512 support - Add automatic dispatch in ggml_vec_dot_i2_i8_s based on operation size - Update build system with BITNET_USE_STFMA option (default: ON) - Add configurable threshold (GGML_BITNET_STFMA_THRESHOLD, default: 1024) - Include test program for verification - Add comprehensive integration documentation Performance improvements: - 2.38× throughput improvement on AVX-512 systems - 4× memory density with 2-bit encoding - Better cache utilization due to smaller footprint Backward compatibility: - Falls back to original implementation for small operations - Can be disabled at compile time with -DBITNET_USE_STFMA=OFF
Replace loop+switch in convert_bitnet_to_stfma_byte() with pure bitwise operations: - Zero branches: eliminates pipeline stalls from branch misprediction - Parallel processing: converts all 4 trits simultaneously - Instruction count: ~5 assembly instructions (AND, SHR, XOR, NOT, SHL, OR) Formula: out_low = in_high (direct copy) out_high = ~(in_high XOR in_low) Performance impact: - Eliminates branching overhead in hot path - Processes millions of conversions per second - Verified correct for all 256 possible input bytes This addresses the critical bottleneck in the conversion function that runs millions of times per second during matrix operations.
Replace costly stack memory round-trip with direct SIMD unpacking:
Before:
int32_t trits[16];
for (int j = 0; j < 16; j++) {
trits[j] = (trit_packed >> (j * 2)) & 0b11;
}
__m512i trit_vec = _mm512_loadu_si512(trits); // Memory round-trip!
After:
__m512i packed_vec = _mm512_set1_epi32(trit_packed);
__m512i shift_amounts = _mm512_setr_epi32(0, 2, 4, 6, ...);
__m512i shifted = _mm512_srlv_epi32(packed_vec, shift_amounts);
__m512i trit_vec = _mm512_and_si512(shifted, mask_2bits);
Performance improvements:
- Eliminates 16 scalar extractions + 1 vector load (AVX-512)
- Eliminates 8 scalar extractions + 1 vector load (AVX2)
- Uses variable shift (_mm512_srlv_epi32/_mm256_srlv_epi32)
- All operations stay in registers, no memory traffic
- Reduces instruction count and improves pipeline efficiency
This addresses the bottleneck in the hot path where trits are unpacked
millions of times per second during matrix operations.
Move all test programs, backup files, and artifacts to a dedicated directory: - Test programs for branchless conversion verification - AVX-512 SIMD unpacking tests - Pattern analysis tools - CMakeLists backup files - Integration test program Add comprehensive README documenting all tests and their purposes. Add .gitignore to exclude compiled binaries and backup files from tracking. This improves project organization and makes it clear which files are development/testing artifacts vs production code.
Comprehensive RFC document for sparse-ternary-fma integration including: - Detailed technical background and motivation - Architecture and implementation overview - Performance benchmarks and memory analysis - Integration design and trade-offs - Questions for maintainers and community feedback - Complete review guide This document can be used to create the PR through GitHub's web interface.
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Subject: Re: [microsoft/BitNet] [RFC]: # "Integration of sparse-ternary-fma for accelerated ternary operations" (PR #365)
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[RFC] Integration of sparse-ternary-fma for accelerated ternary operations
Pull Request Type: Request for Comment (RFC)
Target Repository: microsoft/BitNet
Source Branch: HyperFoldUK:main
Target Branch: microsoft:main
Author: HyperFoldUK maurice.wilson@hyperfold-technologies.com
Purpose
This RFC proposes the integration of the sparse-ternary-fma library into BitNet to significantly accelerate ternary matrix operations through optimized 2-bit encoding and SIMD instructions (AVX2/AVX-512).
Background & Principle
BitNet's 1.58-bit quantization represents weights as ternary values {-1, 0, +1}, enabling extreme model compression while maintaining competitive accuracy. However, the current implementation faces efficiency constraints:
The sparse-ternary-fma library addresses these limitations through:
Why This Matters
Ternary quantization is fundamentally different from traditional quantization. The presence of explicit zeros creates opportunities for sparsity-aware computation that standard quantization approaches cannot exploit. By using 2-bit encoding and SIMD operations, we can:
This Implementation
This fork demonstrates a clean integration:
Architecture
Key Optimizations
1. Branchless Encoding Conversion
Replaces loop+switch with pure bitwise operations:
Impact: Zero branches, processes 4 trits in parallel, ~5 assembly instructions
2. SIMD Trit Unpacking
Eliminates stack round-trip by unpacking directly in registers:
Impact: Eliminates 16 scalar operations + 1 memory load, stays in registers
3. Thread-Local Buffer Pooling
Impact: Zero allocations in hot path after warmup
4. Threshold-Based Dispatch
Impact: Automatic selection based on operation size
Integration Points
Modified Files:
src/ggml-bitnet-mad.cpp- Added automatic dispatch logicNew Files:
include/ggml-bitnet-stfma.h- Adapter layer APIsrc/ggml-bitnet-stfma.cpp- Adapter layer implementation3rdparty/sparse-ternary-fma/- Vendored library (Apache 2.0 licensed)Build System:
CMakeLists.txt- Added sparse-ternary-fma configurationsrc/CMakeLists.txt- Added adapter source filesPerformance
Based on sparse-ternary-fma benchmarks on Intel Xeon with AVX-512:
Benchmark Details
Memory
Encoding Efficiency
Runtime Overhead
Memory Access Pattern
Design
Backward Compatibility
No breaking changes
-DBITNET_USE_STFMA=OFFConfigurability
CMake Options:
Runtime Behavior:
n < threshold: Use original implementationn >= threshold: Use sparse-ternary-fmaTesting
Test Suite Location:
tests/stfma_integration/Coverage:
Test Results:
Code Quality
-Wall -Wextra -WpedanticFull Documentation
Complete technical documentation is available in:
We are seeking feedback from the maintainers and community on:
1. The technical approach and integration design
Questions:
Trade-offs:
2. Performance characteristics on diverse hardware
Needed benchmarks:
Questions:
3. The potential path to upstream adoption
Integration options:
Option A: Optional Feature (Current Approach)
Option B: Native Encoding Change
Option C: Hybrid Approach
Questions:
The code is complete, tested, and ready for review.
We believe this addresses a fundamental efficiency ceiling for ternary computation. By leveraging 2-bit encoding and SIMD acceleration, we can unlock significant performance gains for BitNet models while maintaining full backward compatibility.
What's Included
Complete implementation with all optimizations
Comprehensive test suite with 100% pass rate
Full documentation including integration guide
Backward compatibility with existing code
Configurable behavior via CMake options
Clean commit history with detailed messages
Commit Summary
Integrate sparse-ternary-fma for optimized ternary matrix operations
Optimize encoding conversion with branchless bitwise logic
Optimize AVX2/AVX-512 trit unpacking to eliminate stack round-trip
Organize test files and artifacts into tests/stfma_integration directory
All commits are authored by HyperFoldUK maurice.wilson@hyperfold-technologies.com
Related Work
How to Review
Quick Start
Clone the fork:
git clone https://github.com/HyperFoldUK/BitNet.git cd BitNetBuild with integration:
Run tests:
Detailed Review
STFMA_INTEGRATION_README.mdfor design overviewsrc/ggml-bitnet-stfma.cppfor adapter layersrc/ggml-bitnet-mad.cppfor dispatch logictests/stfma_integration/for verificationContact
For questions or discussions:
We look forward to your feedback and are happy to make adjustments based on maintainer preferences.