Test Update - #14
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The current version (before the incoming merge) has a bug while trying to compile ports/unix. I have to edit the code of the AXTLS library: -------------------------- ssl/os_port_micropython.h -------------------------- #define TTY_FLUSH() -#include "../../../extmod/crypto-algorithms/sha256.h" #define SHA256_CTX CRYAL_SHA256_CTX |
Expose SNVS LP General Purpose Registers as machine.mem_backup with word-level access (itemsize=4). Register count varies by chip (4 on RT1011/RT1176, 8 on RT1015/1021/1052/1062/1064). Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
On families with dedicated backup SRAM (F4, F7, H5, H7, U5, N6), expose 4-8 KB of byte-addressable battery-backed SRAM as machine.mem_backup with itemsize=1. The BKPSRAM clock and backup regulator are enabled during boot after RTC init. On H7 and N6, an MPU region marks the BKPSRAM non-cacheable since its address falls in the default-cacheable SRAM range. On families without BKPSRAM (L0, L1, L4, G0, G4, WB, WL), fall back to RTC backup registers (BKPxR / TAMP BKPxR) with word-level access (itemsize=4, 20-128 bytes). Gated on MICROPY_HW_ENABLE_RTC. Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
Expose the watchdog scratch registers (scratch[0..3] and scratch[5..7], skipping scratch[4] which pico-sdk uses for reboot bookkeeping) as machine.mem_backup, with word-level access (itemsize=4, 28 bytes total across two regions). On RP2350 an additional 32-byte powman scratch region is exposed. Data persists across soft resets but not power-off (no battery backing). Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
Expose the 4KB battery-backed backup SRAM at 0x4902C000 as machine.mem_backup with word-level access (itemsize=4). The region lives in peripheral space and does not support sub-word writes, so the memoryview is exposed as uint32 to enforce word-aligned access from Python. Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
Expose the RTC user memory (2048 bytes default) as machine.mem_backup with byte-level access alongside the existing RTC.memory() method. The two APIs share the same backing buffer but have independent semantics: mem_backup is a raw memoryview while RTC.memory() tracks written length. Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
Expose the 8KB backup RAM at 0x47000000 as machine.mem_backup with byte-level access (itemsize=1) on SAMD51 boards. Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
Add documentation for the machine.mem_backup function including per-port storage sizes, reserved register table, uctypes integration example, and availability. Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
When writing a big-int value to an array, memoryview, or struct buffer, mp_binary_set_val_array and mp_binary_set_val previously used mp_obj_int_to_bytes_impl which writes individual bytes. On hardware registers and peripheral-backed memory that only supports word-sized stores (e.g. STM32 RTC backup registers, NXP SNVS LPGPR, RP2 watchdog scratch), byte-wise writes silently corrupt the target word. For element sizes that fit in mp_int_t, route big-int values through mp_obj_int_get_truncated and then through the same typed store paths that small-int values already use. This is also slightly faster since it avoids the byte decomposition loop in mpz_as_bytes. The byte-wise path is retained for element sizes exceeding mp_int_t (e.g. int64 on 32-bit targets). The bug only manifests on 32-bit targets where values >= 0x40000000 exceed the small-int range and the destination rejects sub-word stores. On 64-bit hosts all uint32 values are small ints and already take the typed-store path. Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
The coverage_32bit job was building with coverage flags but never running gcov or uploading to codecov, so all reported coverage was from the 64-bit build only. Add the same gcov + codecov-action steps that the 64-bit job has, with distinct flags so codecov can merge the data correctly. This closes coverage gaps in code paths that only execute on 32-bit targets (e.g. py/binary.c byte-write fallbacks for typecodes where size > sizeof(mp_int_t)). Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
Exposes NRF_POWER->GPREGRET and GPREGRET2 as two separate word-access regions (4 bytes each). Both registers survive soft reset and watchdog reset. On boards with a UF2/Adafruit bootloader, region 0 (GPREGRET) may be overwritten on bootloader entry. Signed-off-by: Andrew Leech <andrew@alelec.net>
This file is shared by mpy-cross.vcxproj, where PyVariant will be not set (because common.props explicitly doesn't set it when building mpy-cross). Update common.props to only add the variant path to PyIncDirs if not building mpy-cross. This work was funded through GitHub Sponsors. Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
This commit modifies the mapping between predefined value holders and their associated static CPU registers. Temporary values marked as `REG_TEMP0`, `REG_TEMP1`, and `REG_TEMP2` were associated with three caller-save registers (T1, T2, and T3 respectively). Whilst this works, these registers cannot be mapped to the restricted registers set used by most compressed opcodes, leaving potential size optimisations on the table. If those values are mapped to A4, A5, and A6, it means that both `REG_TEMP0` and `REG_TEMP1` have more chances to trigger a compressed opcode (the involved registers window only covers S0, S1, and A0 to A5). This requires no external changes as those registers are caller-saved as well. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit reduces the code needed to emit an indirect load opcode, removing usage of a byte table to hold a width-dependent value to inject in the opcode, in favour of packing the table into a single 16-bits constant that gets shifted and masked when needed. These changes reduce the footprint of the QEMU/VIRT_RV32 firmware by 7 bytes. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit lets native modules targeting the x64 architecture to be built on non-x64 hosts in the same way as on x64 hosts. Since a long time, GCC distributions built to target the same architecture as the host system are available both as regular binaries without any architecture prefix, and as explicit cross-compiler binaries as well. So, on an x64 Linux host the user can build code using either `gcc` or `x86_64-linux-gnu-gcc`, obtaining the same result. This fact is leveraged to always pick the more specific form of the compiler prefix so on AArch64 x64 natmods can be built the same way as long as an x86-64 cross compiler toolchain is available. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit expands the Linux-based QEMU architecture targets to also allow testing x64-built binaries on all architectures whose Linux distribution contains an x86-64 toolchain. These changes are meant to allow AArch64/RV64/etc CI runners to be able to also test the x64 version of the Unix port. This way not only bare-metal ports are tested in an architecture-neutral way, but also the Unix port as well. This is meant to selectively skipped by CI if the test runner is executed on an x64 machine, although for the sake of completeness (and simplicity) all target architectures could be tested on all available runner architectures. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit adds a GC helper for PowerPC 64 bits, providing only the C implementation of the registers value gatherer. The code operates on registers R14 through R31, as mentioned in §2.2.1.1 "Register Roles" from the "OpenPOWER ABI for Linux Supplement Power Architecture 64-Bit ELF V2 ABI" document. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit updates the PowerPC port's garbage collector to use the CPU-tailored GC helper instead of manually collecting roots without using the CPU registers. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit modifies the QEMU makefile to link the final ELF binary through the dedicated linker binary that comes with the toolchain used, instead of performing the linking via GCC. Such a change is needed to let the PowerPC QEMU port to link since it uses a slightly non-standard linkerscript requiring certain options that do not get interpreted correctly when linking binaries via the PowerPC toolchain's compiler binary. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit modifies the QEMU port makefile to allow the QEMU binary to pick the correct binary image depending on which architecture is supposed to be executed. With the introduction of PPC64 to the list of supported architectures, the existing command line needs more customisation capabilities. The PPC64 architecture image being built is actually the BIOS, not an ELF kernel image. QEMU uses a different command line argument to load a machine BIOS versus an ELF kernel image. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit lets platforms or boards override the default MicroPython interpreter stack size, as it was hardcoded to 10240 bytes otherwise. Following `MICROPY_HEAP_SIZE`, a new configurable value called `MICROPY_STACK_SIZE` can now be provided either in a board configuration makefile or via the make command line. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit refactors `basics/string_fstring.py` to extract the part of the test that requires floating point support into its own file under the `float/` tests directory. The QEMU/PPC64 port currently supports F-Strings but has no floating point support enabled as well. Such a combination was not taken into account and thus the test would fail at the very end on that port. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit adds support for the POWERNV9 QEMU board, emulating a PowerPC POWER9 system. The board can be interacted with using the same Makefile targets as the other boards, by using `POWERNV9` as the `BOARD=` argument value. Given the current toolchain state, right now floating point support is not enabled, as the toolchain expects to either use a Linux-compatible standard library running under a proper OS, or to not use any standard library at all (meaning we have to provide our own). There are plans to introduce an on-demand built version of either newlib or picolibc, but they will involve a series of commits that will be submitted later on. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit adds the PPC64 variant of the QEMU port to the list of targets to be tested as part of the CI process. The target is limited to regular test runs, as it has no native modules support and no native emitter. This means the example natmods cannot be tested against the built interpreter, and the full test run also includes executing the standard suite of tests after being compiled via the native emitter backend. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit removes the stand-alone PowerPC port from the MicroPython source tree. Now that QEMU gained support for PPC64 images, it makes little sense to keep the standalone PPC64 port around - especially since said port has been sort of neglected in the past years. Given that the QEMU port is routinely tested there are more chances for the PPC64 architecture to be better supported this way rather than in its previous incarnation. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
- mpconfigport.h: Configure the CAN include file. - alif-mk: Add the fdcan.c driver to the soucr list. - Makefile: Export $(BOARD) to alif.mk. Signed-off-by: robert-hh <robert@hammelrath.com>
For both the OPENMV_AE3 and ALIF_ENSEMBLE boards. - mpconfigboard.h: Specify the CAN name "CAN1" and numbers. - pins.csv: Add the CAN_RXD and CAN_TXD pin names. - ensemble_pin_alt.csv: Add the CAN pin ALT symbols - mphalport.h: Add the CAN enum symbols. The CAN interface pins: ALIF_ENSEMBLE: P12_4 for RX and P12_5 for TX. OPENMV_AE3: P0_4 for RX and P0_5 for TX. The OPENMV_AE3 board has 1.8V/3.3V level shifters at these pins. Signed-off-by: robert-hh <robert@hammelrath.com>
Just one device, no arguments. Signed-off-by: robert-hh <robert@hammelrath.com>
- multi_extmod/machine_can_04_tx_order.py: Skip for Alif, since the Alif port has an opaque send queue which provides no information of the slot number of a message in the TX queue. - multi_extmod/machine_can_05_tx_prio_cancel.py: Skip for Alif, since the Alif port has an opaque send queue which does not allow specific cancels and provides no information of the slot number of a message in the TX queue. - tests/multi_extmod/machine_can_07_error_states.py: Swap the order of resetting the baud rate and restart(). If restart() happens before resetting the baud rate, then the REC counter increases fast and the bus state switched to PASSIVE before the baud rate can be fixed. - tests/multi_extmod/machine_can_07_error_states.py: Add a delay after sending the message "PAYLOAD" avoiding a collision with the test broadcast messages. - multi_extmod/machine_can_08_init_mode.py: Cater for error frames not being reported in SILENT mode. Signed-off-by: robert-hh <robert@hammelrath.com>
Signed-off-by: robert-hh <robert@hammelrath.com>
Enable the LAN9118 driver, networking and lwIP. Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
Enable the LAN9118 driver, networking and lwIP. Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
MPS2_AN500 now enables lwIP networking, which needs the lib/lwip submodule. Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
soft_timer_remove() is a safe no-op on an entry that was never inserted (or that was already removed). Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
When tcp_write() returns ERR_MEM, lwip_tcp_send() retried on a flat 50ms delay. During that sleep nothing drives lwIP forward, so the condition the retry is waiting for (ACKs arriving and freeing queued segments) is only resolved by background polling, and every write that hits this path is stalled for a fixed 50ms. On any configuration whose lwIP heap is small relative to TCP_SND_BUF this becomes the dominant cost and caps TCP transmit throughput at roughly write_size per 50ms, with the socket reporting no error at all. Poll the stack via poll_sockets() (which includes a 1ms wait) instead of sleeping blindly, and time the retry loop out after 10 seconds using mp_hal_ticks_ms(), matching the sndbuf waiting loop above. Measured on an OpenMV RT1060 (CYW4343W WiFi, MEM_SIZE smaller than TCP_SND_BUF): sustained TCP transmit from a Python socket benchmark sat at a constant 1.3Mbit/s -- exactly its 8KB writes paced by the 50ms sleep. With this change the same benchmark reaches 14.4Mbit/s, and configurations with adequately sized heaps are unaffected. Signed-off-by: Kwabena W. Agyeman <kwagyeman@live.com>
With gcc 16.2.0, warnings about old-style function definitions popped up when building with cmake. This fix suppresses these warnings for gcc, and reportedly also helps with certain versions of clang as well. See also #19644. Signed-off-by: Stefan Kratochwil <Kratochwil-LA@gmx.de>
Using `board.md` is the standard (and only) way to add information about a board to the top of its download page. The `board.md` file is processed by `tools/autobuild/build-downloads.py`. A lot of boards already use this facility, but some had stray markdown files named `readme.md` and `README.md`. Rename those files to `board.md` so their contents appears on the board download page. Signed-off-by: Damien George <damien@micropython.org>
machine_can_04_tx_order: - remove the SKIP and the additional comment at the test head. machine_can_05_tx_prio_cancel.py: - remove the SKIP and the additional comment at the test head. - instance0 retries a send attempt until it succeeds. Otherwise instance0 may stop "babbling" prematurely at a fast MCU. Signed-off-by: robert-hh <robert@hammelrath.com>
With the new TX queue the index of messages in the queue is known, reported bye can.send() and can be used by can.cancel_send(). That makes the respective note obsolete. The note about the value of pending RX messages is still valid. Since that applies to the MIMXRT port as well, it was added. Signed-off-by: robert-hh <robert@hammelrath.com>
If the firmware is built with DEBUG=1, a printf() statement gets active in main.c, which is not declared. Use mp_printf() instead. Signed-off-by: robert-hh <robert@hammelrath.com>
Instead of using the hardware TX FIFO. The software queue: - provides the slot number for a TX message - allows to cancel a specific message, and - allows to count the number of messages in the queue and report it with CAN.get_counters(). The bit sequence in the tag to determine a message priority is identical to the transmission sequence for proper arbitration. A mechanism is implemented to replace a message waiting to be sent, if a message with higher priority is added to the queue. With these changes, CAN support passes all CAN tests from tests/multi_extmod for the Alif port either as instance 0 or instance 1 with a minor exception: In about 1 of 100 attempts test machine_can_05_tx_prio_cancel.py "failed" with the Alif board as instance 0, which is the uncritical instance. The fail pattern shows a low prio message which was sent ahead of the hi-prio ones. Messages that already started the transmission cannot be cancelled any more. Signed-off-by: robert-hh <robert@hammelrath.com>
The WL_IRQ line from the CYW43 is configured falling-edge triggered, but the chip holds the line asserted (low) for as long as it has pending frames. Under sustained receive the line never returns high between frames, so no new falling edge is generated after a poll that does not fully drain the chip, and the wakeup is lost. Configure the pin level-low sensitive instead. A level trigger would re-fire continuously until PendSV gets to run the poll, so the handler masks the GPIO interrupt after scheduling, and a new post-poll hook (CYW43_POST_POLL_HOOK, already provided by cyw43-driver and used the same way by the rp2 port) clears and unmasks it after every poll: if the line is still low the interrupt immediately re-raises, so wakeups cannot be lost regardless of how many frames are pending. Tested on an OpenMV AE3 (CYW43439 on SPI): WLAN scan/connect/traffic all behave as before, verified with the driver's stats counters that the interrupt path services every received frame. Signed-off-by: Kwabena W. Agyeman <kwagyeman@live.com>
The CYW43 gSPI interface is specified up to 50MHz but the bus was run at
16MHz. Simply raising the clock fails: at 24MHz and above the chip's
firmware download breaks ("Failed to start CYW43"), because the MISO
round-trip delay exceeds the controller's default sample point. Set the
SPI RX sample delay to 2 spi_clk cycles to move the sample point, which
makes 32MHz operation reliable (verified across repeated WLAN bring-up
and traffic cycles on an OpenMV AE3).
Signed-off-by: Kwabena W. Agyeman <kwagyeman@live.com>
The 8*MSS TCP window and send buffer limit TCP throughput to window/RTT, which on WiFi round-trip times is below what the link and the CYW43 can carry. Double both to 16*MSS and raise MEM_SIZE to 48K so the heap comfortably covers the send buffer (lwIP's ERR_MEM retry path otherwise dominates). The Ensemble parts have ample SRAM for this. Measured on an OpenMV AE3 (CYW43439): TCP receive from a Python socket benchmark improves ~15-20%, transmit similarly; UDP is unaffected. Signed-off-by: Kwabena W. Agyeman <kwagyeman@live.com>
This minor fix allows alif boards to be built when there is a space in the absolute path for the repository. Signed-off-by: Damien George <damien@micropython.org>
The RX programmable burst length was left at its reset value of zero, so the RX DMA transferred received frames from the MTL RX FIFO to memory in minimal bursts and could not keep up with 1Gbit line rate: under a sustained TCP RX stream the 4KB MTL RX FIFO overflows (the MTL RX overflow counter increments) even while free RX descriptors are available, capping TCP RX throughput at ~50Mbit/s on an OpenMV N6. The TX path already programs a burst length; set the RX side to 32 beats to match the FIFO drain rate to line rate. Verified on an OpenMV N6 (RGMII, 1Gbit link) with the MTL RX queue overflow counter (MTLRXQ0MPOCR) and iperf-style Python benchmarks: this change and the AXI outstanding-request limit change together stop the FIFO overflows at line rate. Signed-off-by: Kwabena W. Agyeman <kwagyeman@live.com>
The DMA system bus mode register's read and write outstanding-request limit fields reset to zero (one outstanding AXI request), which serialises the RX DMA's memory writes and, combined with the burst length, determines how fast the MTL RX FIFO can drain. At 1Gbit line rate one outstanding request is not enough: the 4KB FIFO fills in a few frame times whenever a burst arrives and the MTL drops frames (RX overflow counter increments) even though free RX descriptors are available. Set both limits to their maximum of 4 outstanding requests. Together with programming the RX burst length this lets the RX DMA sustain line rate on an OpenMV N6 (RGMII, 1Gbit link), verified with the MTL RX overflow counter and Python socket benchmarks. Signed-off-by: Kwabena W. Agyeman <kwagyeman@live.com>
The STM32N6 MAC is configured with checksum offload enabled (MACCR.IPC), so the hardware verifies incoming IPv4 header and TCP/UDP/ICMP payload checksums, and because the MTL RX queue operates in store-and-forward mode with forward-error-packets left disabled, frames that fail those checks are dropped before they reach the driver. lwip was nevertheless re-verifying every RX checksum in software, and because this driver runs lwip's input path directly in the ETH IRQ handler, that work is done at interrupt priority for every received frame. Keep only the software ICMP checks (cheap and rare) and drop the redundant IP/UDP/TCP ones on STM32N6. Other MCUs are unchanged, as they do not enable MACCR.IPC. On an OpenMV N6 (RGMII, 1Gbit link) this raises sustained TCP RX throughput measured from a Python socket benchmark by a further ~30%, with TCP TX, UDP TX and UDP RX rates unchanged. Signed-off-by: Kwabena W. Agyeman <kwagyeman@live.com>
On ARMv8-M parts the bootloader can hand control to the application with the MPU still enabled: the OpenMV N6 bootloader was observed to do so, with CTRL=ENABLE|HFNMIENA|PRIVDEFENA and its own MAIR attributes still in place. mpu_init() then rewrote MAIR0, region 0 and finally CTRL while the MPU was live and code was executing from external XSPI flash. Reconfiguring a live MPU under XIP raises a spurious MemManage fault (IACCVIOL) on the Cortex-M55 within a few instructions of the CTRL write, but only when an instruction fetch happens to fall inside the reconfiguration window -- so whether a given firmware boots depended on its code layout. Several OPENMV_N6 builds of current master fault on every boot (parked in MemManage_Handler at reset, CFSR=IACCVIOL, before reaching main), while other builds of the same source boot cleanly. Fix by putting the MPU into a defined state first: disable it (with DSB/ISB), clear every region, then configure MAIR0 and region 0 and enable it. With this change previously non-booting layouts boot reliably (verified over repeated resets on an OpenMV N6), and layouts that already worked are unaffected. Signed-off-by: Kwabena W. Agyeman <kwagyeman@live.com>
TCP receive throughput is bounded by window/RTT. At the ~5-6ms round-trip time of the OPENMV_N6's CYW43439 WiFi link, the 16*MSS window works out to ~31Mbit/s -- and that is exactly what the board measures, well below what the link otherwise carries (~43Mbit/s UDP on the same air). Double the receive window to 32*MSS: it is covered by the existing PBUF_POOL (32 buffers), so there is no additional static memory cost, and the send buffer is unchanged. Measured on an OpenMV N6 (Python socket benchmark, 2.4GHz, same board/AP/position): TCP receive over WiFi improves from ~31Mbit/s to 35-39Mbit/s; TCP transmit and UDP are unchanged, and ethernet on the same board is unaffected (its sub-millisecond RTT was never window-limited). Signed-off-by: Kwabena W. Agyeman <kwagyeman@live.com>
The port used the smallest lwipopts_common.h memory tier: MSS=800, an 8*MSS=6400 byte window and an 8000 byte heap. On WiFi round-trip times that window caps TCP at window/RTT, and the sub-MTU MSS costs per-packet efficiency on every link. Measured on an OpenMV RT1060 (CYW4343W WiFi): TCP was limited to 6.4Mbit/s transmit / 15.9Mbit/s receive. Switch to MSS=1460 with a 7*MSS receive window, 6*MSS send buffer and a 13K heap (sized so the heap comfortably exceeds the send buffer, keeping lwIP's ERR_MEM retry path cold). With this configuration the same benchmark measures 22.2Mbit/s transmit / 24Mbit/s receive (3.5x / 1.5x), with UDP unaffected. 100M ethernet on the same silicon still runs at line rate. All values are guarded so a board can override them, and only boards with a network interface build lwIP on this port. Signed-off-by: Kwabena W. Agyeman <kwagyeman@live.com>
The RTC prescalers were fixed at compile time via RTC_ASYNCH_PREDIV and RTC_SYNCH_PREDIV, sized for a 32768Hz LSE. When the RTC actually runs from the ~32kHz LSI -- because the LSE failed to start, or because a bootloader configured it that way before MicroPython ran -- the same divider leaves the RTC about 2.3% slow (over half an hour per day), far beyond what rtc.calibration() can correct. Select the prescalers at startup for the clock source the RTC actually uses: RTC_x_PREDIV_LSE (defaulting to the existing RTC_x_PREDIV values) when running from the LSE, and RTC_x_PREDIV_LSI (defaulting to a divide by the LSI's nominal 32000) when running from the LSI, whether found already running, chosen at fresh init, or entered via the LSE-failure fallback. The existing wrong-prescaler repair path now also targets the selected values, so moving between sources corrects the divider without losing the date and time. The subsecond/microsecond conversions previously baked RTC_SYNCH_PREDIV in at compile time; they now use the runtime prescaler (with 64-bit intermediate math, exact for any prescaler value) so subseconds stay correct for whichever source is in use. Measured on an Arduino Nicla Vision (RTC held on the LSI by its stock bootloader): the timekeeping error improves from -22300ppm to -684ppm, with the remaining part-specific LSI offset trimmable via rtc.calibration(). Signed-off-by: Kwabena W. Agyeman <kwagyeman@live.com>
The Arduino Giga, Nicla Vision, Opta and Portenta H7 have an accurate external 32768Hz oscillator (a SiT1532, +-20ppm) on OSC32_IN, but their stock Arduino MCUboot bootloader is built with Mbed's lse_available disabled and reinitialises the RTC onto the LSI at every hard reset when it finds any other clock source selected -- and the backup-domain reset that requires wipes the calendar. Verified on a Nicla Vision: with the RTC switched to LSE bypass (which does start and keep +-0ppm time while running), every machine.reset() and deep-sleep wake came back on the LSI with the calendar reset to the bootloader's 2021-01-01 epoch. So these boards run the RTC from the LSI, but the prescalers divided by 32768, making the RTC about 2.3% slow -- over half an hour per day, far beyond what rtc.calibration() can correct. Set the LSI prescalers to divide by the LSI's nominal 32000 instead, and drop the MICROPY_HW_RCC_RTC_CLKSOURCE override so the runtime prescaler selection sees whichever source the bootloader provides: boards updated to an LSE-enabled bootloader get the SiT1532 with 32768Hz prescalers automatically, everything else stays on the corrected LSI. Tested on an Arduino Nicla Vision (stock bootloader): -684ppm over 240s measurements against the HSE-derived SysTick (previously -22300ppm measured over two hours against NTP), time preserved through machine.deepsleep(20000) and machine.reset(), and the microsecond subsecond fields still exact (32000/64 = 500). Signed-off-by: Kwabena W. Agyeman <kwagyeman@live.com>
If `_thread.start_new_thread` fails to allocate stack space because of MemoryError, it leaves the environment stuck in a way that appears to have a thread running on core1. Later, when memory is available, `start_new_thread` will continue to fail because it will appear that core1 is in use. To remedy this, the `core1_entry` pointer is not setup until after the stack space is successfully allocated. Signed-off-by: Jared Hancock <jared.hancock@centeredsolutions.com>
This commit adds board support for the Seeed XIAO SAMD21 Plus to the samd port. It reuses the existing SEEED_XIAO_SAMD21 standard board definition, which is the same except for additional pins. Note that the pin names "A0_D0" etc has been removed and replaced with individual names "A0", "D0" etc. Signed-off-by: cumin <13809292481@163.com>
Expose zepyhr regulator api. Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The machine_timer_obj_head linked list is updated from thread context when a timer is created or deinitialised, and from IRQ context when a one-shot timer expires: machine_timer_callback() runs in the k_timer expiry function and calls machine_timer_deinit() to unlink the timer. A timer expiring while the main thread is in the middle of inserting or unlinking an entry can corrupt the list, losing timers or leaving it circular so a later traversal never terminates. Guard both places that touch the list with MICROPY_BEGIN_ATOMIC_SECTION and MICROPY_END_ATOMIC_SECTION, which on this port are irq_lock() and irq_unlock() and so nest safely when machine_timer_deinit() is reached from the expiry function. Fixes issue #18728. Signed-off-by: Calin Faja <calinfaja@gmail.com>
Commit 6bde1b5 removed this configuration because TinyUSB 0.21.0 no longer uses it. But the esp32 port still uses an older TinyUSB version/fork (based on TinyUSB 0.18.0) and therefore still needs this runtime CDC configuration. Signed-off-by: Damien George <damien@micropython.org>
run-perfbench -s fails when benchmark result contains tests that are skipped with "too large". To fix this issue, skip line that contains "skipped: " and "skipped because they are too large: " using regular expression. Signed-off-by: Yuuki NAGAO <wf.yn386@gmail.com>
This commit tweaks `mpy-tool.py`'s printout of qstr strings when disassemblying a MPY file. Now strings will be printed with non-printable and control codes being quoted (using Python's `repr()`), and containing a special marker in case a qstr is encoded as an index in the static qstr table. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
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