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feat(M4-P0E2A): compile exact Studio 3-MU SCD roster to atomic ARM3 V2 binary - #344
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Cache exact three profiles and identity hash from SCD-selected family and per-MU VLAN overrides. Reject invalid identities and layouts; exercise round-trip and isolation on Linux/Windows native Qt and matched preview CI. No device writes; preserve M3.H.3.
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SclProfileModelwith cached canonicalARM3V2 envelope and firmware-equivalent full-envelope FNV identity hash. Compile from the three existing validated UI profiles, preserving SCD MAC/svID/APPID, SCD VLAN0/PCP4 and any intentionally configured per-MU VLAN override.M4SclCompileHarness.cpptest using reference 3-MU SCD: explicit 9-2LE selection, ARM3 roundtrip and CRC, correct all three identities/repeated APPID 0x4000, full-envelope hash matching firmware, MU2 VLAN override leaves MU1/MU3 untouched, deterministic re-encoding, invalid-family/clear fail-closed.Scope/gates
This is P0E2A host compile only, NOT yet deployment,
MULTISVwire handshake, readback adoption, or verified M4 START. Those follow in P0E2B/C. No new realtime clocks/tasks or changes to M3.H.3 Official Stable. See #333, ARD M4, and merged P0E1 #343.Do not merge until exact-head CMake/Qt/native preview and firmware CI pass.