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feat(M4-P0D2): wire isolated MU1/MU2/MU3 setpoints into ESP32 triple-SV TX - #341
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Connect existing independent 3×4I4V signal banks to the actual opt-in triple-SV publisher. Add
SVSTREAM <1..3> SET|FREQ|SHOWcontrols with per-stream validation, generation and readback. No separate timer/RTOS worker, legacy single-SV unaffected. CI must pass ESP32-P4 firmware build and C++ GCC/Clang/MSVC. Not yet a multi-command scenario transaction or Studio pagination. Seedocs/M4_P0D2_STREAM_SETPOINT_CONTROL.mdand #333.