[masarray]

Draft consumer integration atop exact #494, with exact engine PR #157 pinned. Keeps P0 frozen 64-page fast scan. Runs second bounded targeted LN GVA pass only from wire-confirmed DataSet ST/MX members, then builds canonical live model once from the combined type results. No dynamic dataset writes, cyclic process polling, changed control/Command Shout, or additional association. Baseline #494 remains untouched. Qualification requires Windows CI, exact F650 30/30 EVEGGIO and 16/16 CSWI feedback, 13 measurement phases, and report continuity checked separately.

[masarray]

P7.6G exact-HEAD CI and field candidate (2026-10-10)

ARSAS head: e0d63a9b8cd1dfb4b6c8321044363a283014b329 on draft PR #497, atop PR #494. Engine head: 8b0c0f7e695b016834e40a6f068994dcc945cb1a on draft ARIEC61850 PR #157, pinned exactly in consumer lock. Historical previousTrialPin restored unchanged to physical P0-5b engine 4467124775d8d9d76f3db194f9fbfd97144767a8, and P6.2 trial recorded separately; no historical authority rewritten.

Core implementation: Frozen fast GetNameList budget remains 64 pages; extra GVA probes are rooted exclusively in observed successful configured DataSet ST/MX members, deduplicated against attempted LN roots, same MMS association and negotiated window, with new LN paths admitted only after successful exact root type reply + DataSet member evidence. Consumer merges initial and closure types before building one canonical live model. Static reporting remains RCB report-only; no cyclic MMS process polling, no dynamic DataSet writes, no control changes.

CI evidence: Native Build ARSAS run #37997481084 SUCCESS: Windows compile, application regression tests, portable publish, portable EXE smoke and artifact upload all successful. Exact portable EXE artifact #11647229638. Field Capture run #37997481087 SUCCESS, artifact #11647279447. SCL Interoperability R7, Merge Execution, Provenance, Golden Budget, Repeat-Run, Reference Guard, IO List and SV validation succeeded. Mainline Readiness intentionally FAILS since trial pin is not physical-qualified; do not weaken/bypass it. Windows installer validation may finish separately.

Acceptance pending: do NOT mark discovery parity or release accepted until new F650 field diagnostic proves 30/30 EVEGGIO, 16/16 CSWI feedback, 13 phase magnitudes plus AuxV, exact 67 signal reference parity (modulo separately explained explicit selection), six RCB routed actual reports, and no BRCB continuity regression. Compare exact reference sets, not counts alone. Zero polling/dynamic DataSet writes and unchanged command canonical path are mandatory. Keep drafts unmerged; never treat CI as physical verification.

[masarray]

D28 archival: old F650/IEC 61850 interoperability prototype is no longer an open PR integration candidate. The operator's more recent successful evidence and accepted ARSAS baseline supersede the prior iteration; the operator will NOT perform a new capture to qualify historic branches. Closing this PR unmerged preserves exact HEAD e0d63a9b8cd1dfb4b6c8321044363a283014b329, all captured discussion and patch for traceability. Its unique code is not presumed present in the current RC, and closure is not a declaration of new R7/R10 hardware qualification. Working build, main branch, engine lock and stable release are untouched.