Hi! I'm Jason, a 2nd year computer engineering student. I have a passion for all things computer hardware, and I love writing Verilog. If you want to check out my most recent ongoing project, it is a SystemVerilog RISC-V 64 bit CPU core, with a 7-stage pipeline, virtual memory, and (partial) SVA formal verification. Coming in the future: superscalar processing, out-of-order pipeline, and more advanced features that come with that like a load-store queue, cache coherency, etc.
I also have an ongoing research project, TAILOR, which involves the automated creation of application specific processors, as well as a superoptimization-based program rewriting approach to support a modified ISA, for the purpose of reducing power consumption.
I've implemented a small, single-cycle ARM32 core, as well.
Finally, you can check out my Python library, BaseballQuery, which rapidly and efficiently processes data using SQL queries to quickly calculate all the stats in baseball history, from Retrosheet and MLBAM data.