Fix silent motor/servo outputs from shared advanced-timer DMA request lines on 29 targets

[sensei-hacker]

Summary

TIM1/TIM8 CH1-CH3 on F4/F7 can select either a per-channel dedicated DMA
request line or a combined CH1/CH2/CH3 line shared with sibling channels.
When a sibling channel is also genuinely driven, its compare events land on
the shared line too and corrupt this channel's DSHOT transfer -- silently,
with no boot-time error or CLI diagnostic. This is the same defect class
fixed once before upstream in ab07785fa9 ("Fix channel selection for DMA2
Stream6"), applied there to 4 targets. This PR fixes 29 more targets found
by a full-tree sweep.

Changes

Each target gets a one-line-per-channel dmavar change in target.c,
moving the affected channel(s) off the shared/combined DMA request line
onto their own dedicated one (or, on TMOTORF7, the reverse correction --
its F7 header table orders the dedicated/combined options oppositely from
F4's, and the existing value had picked the combined one by F4 convention).

Two targets could not be fully resolved: BEEROTORF4 and DALRCF722DUAL
each have a pair of outputs whose only non-combined DMA route is the
identical physical DMA stream -- a genuine hardware DMA-topology conflict,
not fixable by any dmavar choice. In both cases the S1-S4 (basic-quad)
output was kept clean; the other, already-broken output is unchanged.

Testing

• Verified with a Python simulation of INAV's actual pwm_mapping.c role-
  resolution and DMA-claim logic (motor-count sweep per target): every
  target's SHARED_TIMER_DMA_REQUEST hazard clears (or, for the 2
  irreducible cases, only the non-S1-S4 output remains flagged), and no new
  DMA_STREAM_COLLISION/SILENT_DEAD_MOTOR hazard was introduced anywhere
  in the sweep, on any of the 29 targets.
• Full-tree resweep (188 F4/F7/AT32 targets) confirms no unrelated
  regression; BEEROTORF4 specifically improves from a CERTAIN hazard (an
  S1-S4 output actually dead) to NOTICE (only a non-critical output
  affected).
• Built 6 representative targets spanning both MCU families, both fix
  directions, and both partial-fix cases (AIKONF4, BEEROTORF4,
  TMOTORF7, DALRCF722DUAL, PIXRACER, FRSKYPILOT) -- all compiled
  cleanly with no warnings or memory-region overflows.
• Not hardware-tested. I don't have physical boards for any of these
  29 targets. The fix pattern is identical to the previously
  hardware-confirmed ab07785fa9 fix, and is verified against the real
  DMA-routing option tables and the actual firmware role-resolution logic,
  but the specific boards here have not been flight-tested with this
  change. Flagging "Testing Required" for anyone with matching hardware to
  confirm.

Related Issues

None filed; found via static analysis while investigating the
ab07785fa9 defect class across the full target tree.

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PR Summary by Qodo

Avoid shared TIM1/TIM8 DMA request lines to prevent silent DSHOT output loss

🐞 Bug fix ⚙️ Configuration changes 🕐 20-40 Minutes

AI Description

• Switch affected TIM1/TIM8 CH1-CH3 outputs to dedicated DMA request variants on 29 targets.
• Prevent silent DSHOT corruption when sibling channels drive the combined CH1/CH2/CH3 DMA line.
• Keep known-unavoidable DMA topology conflicts unchanged while protecting primary S1–S4 outputs.

Diagram

graph TD
  A["Per-target \"target.c\" (29)"] --> B["DEF_TIM dmavar"] --> C["Timer DMA map"] --> D["pwm_mapping.c"] --> E(("TIM1/TIM8 CH1-CH3")) --> F[("DMA stream")] --> G["DSHOT waveform"]
  subgraph Legend
    direction LR
    _cfg["Config / tables"] ~~~ _hw(("Hardware")) ~~~ _dma[("DMA")]
  end

Loading

High-Level Assessment

The following are alternative approaches to this PR:

1. Add runtime/boot-time hazard detection for shared-request usage

• ➕ Catches future target-table mistakes automatically
• ➕ Turns a silent failure into a diagnosable error/warning
• ➖ Adds code paths and UX decisions (warn vs hard-fail)
• ➖ Still requires target-table corrections for best behavior

2. Normalize DMA-map variant ordering across STM32 families

• ➕ Avoids F4-vs-F7 dmavar semantic inversion (e.g., TIM8 CH1)
• ➕ Reduces likelihood of repeating the TMOTORF7-style mis-selection
• ➖ Potentially breaking change for existing targets relying on current ordering
• ➖ Requires careful audit of all current dmavar values

3. Introduce named dmavar constants (DEDICATED vs COMBINED) in target defs

• ➕ Makes target.c intent self-documenting
• ➕ Prevents mistakes from “0/1 means what?” ambiguity
• ➖ Requires macro/API changes across all targets (broad churn)
• ➖ Still depends on correct underlying header tables

Recommendation: The PR’s approach (per-target dmavar corrections) is the lowest-risk fix and directly addresses the failure mode without changing core driver logic. Consider a follow-up improvement to add a lightweight boot-time warning for the specific “advanced-timer combined DMA request line in use with multiple active sibling channels” pattern, to prevent silent regressions and to surface the two irreducible hardware-conflict cases more clearly.

Files changed (29) +52 / -52 · 1 not counted

Bug fix (29) +52 / -52

target.cMove TIM8 CH1–CH3 outputs to dedicated DMA request variant _{not counted}

Move TIM8 CH1–CH3 outputs to dedicated DMA request variant

• Switches TIM8 CH1/CH2/CH3 (S1–S3) dmavar from 0 to 1 so these channels don’t use the combined CH1/CH2/CH3 DMA request line. Prevents sibling-channel activity from corrupting DSHOT DMA transfers.

src/main/target/AIKONFF4/target.c

target.cSelect dedicated DMA mapping for TIM1 CH3N output +1/-1

Select dedicated DMA mapping for TIM1 CH3N output

• Changes TIM1 CH3N dmavar from 0 to 1 to avoid using the shared advanced-timer DMA request line. Reduces risk of silent DSHOT corruption when other TIM1 channels are active.

src/main/target/AIKONF7/target.c

target.cMove TIM8 CH1–CH2 outputs off combined DMA request line +2/-2

Move TIM8 CH1–CH2 outputs off combined DMA request line

• Updates TIM8 CH1 and CH2 dmavar from 0 to 1 so these outputs use dedicated DMA request options rather than the combined CH1/CH2/CH3 request. Aligns with existing CH3 already set to variant 1.

src/main/target/ALIENFLIGHTF4/target.c

target.cSelect dedicated DMA mapping for TIM1 CH3N output (S8) +1/-1

Select dedicated DMA mapping for TIM1 CH3N output (S8)

• Changes TIM1 CH3N (S8_OUT) dmavar from 0 to 1 to avoid shared advanced-timer DMA request behavior. Helps prevent silent output corruption under DSHOT.

src/main/target/ANYFCM7/target.c

target.cMove TIM8 CH3 and CH2N outputs to dedicated DMA request variant +2/-2

Move TIM8 CH3 and CH2N outputs to dedicated DMA request variant

• Updates TIM8 CH3 (S8) and TIM8 CH2N (S10) dmavar from 0 to 1 to select non-combined DMA request variants. Reduces risk of shared-line interference for DSHOT-capable outputs.

src/main/target/ATOMRCF405NAVI_DELUX/target.c

target.cMove selected TIM1/TIM8 outputs to dedicated DMA request variants +3/-3

Move selected TIM1/TIM8 outputs to dedicated DMA request variants

• Changes TIM1 CH2N and CH3N dmavar from 0 to 1 and TIM8 CH2 dmavar from 0 to 1 to reduce shared-request-line hazards. This target is noted as having an underlying DMA-topology conflict for a pair of outputs; this change prioritizes keeping the core outputs clean.

src/main/target/BEEROTORF4/target.c

target.cMove TIM1 CH3 output to dedicated DMA request variant +1/-1

Move TIM1 CH3 output to dedicated DMA request variant

• Updates TIM1 CH3 dmavar from 0 to 1 so it uses a dedicated DMA request option rather than the combined CH1/CH2/CH3 request. Prevents sibling-channel compare events from corrupting DSHOT transfers.

src/main/target/BLADE_F4/target.c

target.cSelect dedicated DMA mapping for TIM1 CH3N output +1/-1

Select dedicated DMA mapping for TIM1 CH3N output

• Changes TIM1 CH3N dmavar from 0 to 1 to avoid using the combined advanced-timer DMA request line. Reduces risk of silent motor/servo output issues under DSHOT.

src/main/target/BRAHMA_F405/target.c

target.cMove TIM1 CH3 output to dedicated DMA request variant +1/-1

Move TIM1 CH3 output to dedicated DMA request variant

• Updates TIM1 CH3 (S7) dmavar from 0 to 1 to select the dedicated DMA request option. Mitigates shared-request-line interference when other TIM1 channels are active.

src/main/target/BRAHMA_F722/target.c

target.cMove TIM8 CH3 and CH2N outputs to dedicated DMA request variants +2/-2

Move TIM8 CH3 and CH2N outputs to dedicated DMA request variants

• Changes TIM8 CH3 (S5) and TIM8 CH2N (S7) dmavar from 0 to 1 to avoid combined DMA request line usage on advanced timers. Helps ensure reliable DSHOT DMA operation when sibling channels run.

src/main/target/COREWINGF405WINGV2/target.c

target.cMove TIM8 CH1 output to dedicated DMA request variant +1/-1

Move TIM8 CH1 output to dedicated DMA request variant

• Updates TIM8 CH1 (S2) dmavar from 0 to 1 to avoid the combined CH1/CH2/CH3 DMA request line. Keeps DSHOT transfers isolated from sibling-channel DMA request activity.

src/main/target/DALRCF405/target.c

target.cMove TIM1 CH1 output to dedicated DMA request variant (partial conflict remains) +1/-1

Move TIM1 CH1 output to dedicated DMA request variant (partial conflict remains)

• Changes TIM1 CH1 (S5) dmavar from 0 to 1 to avoid the combined advanced-timer DMA request line. The target is noted as having a hardware DMA-topology conflict for a pair of outputs; this change focuses on keeping primary outputs clean.

src/main/target/DALRCF722DUAL/target.c

target.cMove TIM1 CH1–CH3 outputs to dedicated DMA request variants +3/-3

Move TIM1 CH1–CH3 outputs to dedicated DMA request variants

• Updates TIM1 CH1/CH2/CH3 dmavar from 0 to 1 so these outputs use dedicated DMA requests rather than the combined CH1/CH2/CH3 request line. Prevents silent DSHOT corruption when multiple TIM1 channels are active.

src/main/target/F4BY/target.c

target.cMove TIM8 CH1–CH3 outputs to dedicated DMA request variants +3/-3

Move TIM8 CH1–CH3 outputs to dedicated DMA request variants

• Changes TIM8 CH1/CH2/CH3 dmavar from 0 to 1 to avoid the shared CH1/CH2/CH3 DMA request. Improves DSHOT reliability when multiple TIM8 channels are driven.

src/main/target/FISHDRONEF4/target.c

target.cSelect dedicated DMA mapping for TIM1 CH3N output +1/-1

Select dedicated DMA mapping for TIM1 CH3N output

• Updates TIM1 CH3N (S3) dmavar from 0 to 1 to select a dedicated DMA request option. Avoids combined request line interference with sibling channels.

src/main/target/FLYINGRCF4WINGMINI/target.c

target.cMove TIM8 CH1–CH3 outputs to dedicated DMA request variants +3/-3

Move TIM8 CH1–CH3 outputs to dedicated DMA request variants

• Updates TIM8 CH3, CH1, and CH2 dmavar from 0 to 1, selecting dedicated DMA request options for these outputs. Reduces risk of DSHOT DMA corruption caused by combined CH1/CH2/CH3 request lines.

src/main/target/FOXEERF405/target.c

target.cMove TIM1 CH1–CH3 outputs to dedicated DMA request variants +3/-3

Move TIM1 CH1–CH3 outputs to dedicated DMA request variants

• Changes TIM1 CH1/CH2/CH3 dmavar from 0 to 1 to avoid combined advanced-timer DMA request usage. Ensures these outputs don’t get corrupted by sibling-channel compare events under DSHOT.

src/main/target/FRSKYPILOT/target.c

target.cSelect dedicated DMA mapping for TIM1 CH2N motor output +1/-1

Select dedicated DMA mapping for TIM1 CH2N motor output

• Updates TIM1 CH2N (M3) dmavar from 0 to 1 to avoid shared DMA request line behavior on the advanced timer. Reduces risk of silent motor output issues when other TIM1 channels are active.

src/main/target/FRSKY_ROVERF7/target.c

target.cMove TIM1 CH2N and TIM8 CH3 outputs to dedicated DMA request variants +2/-2

Move TIM1 CH2N and TIM8 CH3 outputs to dedicated DMA request variants

• Changes TIM1 CH2N (S1_OUT) and TIM8 CH3 (S4_OUT) dmavar from 0 to 1 to avoid combined advanced-timer DMA request line usage. Improves reliability for DSHOT-capable outputs.

src/main/target/IFLIGHTF4_TWING/target.c

target.cMove TIM1 CH1–CH3 outputs to dedicated DMA request variants +3/-3

Move TIM1 CH1–CH3 outputs to dedicated DMA request variants

• Updates TIM1 CH1/CH2/CH3 dmavar from 0 to 1 for S5–S7 outputs to avoid the combined CH1/CH2/CH3 DMA request line. Prevents sibling-channel activity from silently corrupting DSHOT DMA transfers.

src/main/target/IFLIGHT_BLITZ_F7_AIO/target.c

target.cMove TIM8 CH3 and CH2N outputs to dedicated DMA request variants +2/-2

Move TIM8 CH3 and CH2N outputs to dedicated DMA request variants

• Changes TIM8 CH3 (S5) and TIM8 CH2N (S7) dmavar from 0 to 1 to select dedicated DMA request routes. Reduces susceptibility to shared-line DMA request interference.

src/main/target/JHEMCUF405WING/target.c

target.cMove TIM1 CH3 output to dedicated DMA request variant +1/-1

Move TIM1 CH3 output to dedicated DMA request variant

• Updates TIM1 CH3 (S7) dmavar from 0 to 1 to avoid combined advanced-timer DMA request usage. Helps prevent silent DSHOT corruption when sibling TIM1 channels are active.

src/main/target/MAMBAF722_WING/target.c

target.cMove TIM1 CH3 output to dedicated DMA request variant +1/-1

Move TIM1 CH3 output to dedicated DMA request variant

• Changes TIM1 CH3 (S7) dmavar from 0 to 1 to select the dedicated DMA request mapping. Improves robustness of DMA-driven outputs against sibling-channel interference.

src/main/target/MAMBAF722_X8/target.c

target.cSelect dedicated DMA mapping for TIM1 CH1N output +1/-1

Select dedicated DMA mapping for TIM1 CH1N output

• Updates TIM1 CH1N (S2_OUT) dmavar from 0 to 1 to avoid combined DMA request line behavior. Reduces risk of silent output corruption for DMA-driven protocols.

src/main/target/NOX/target.c

target.cMove TIM1 CH1–CH3 outputs to dedicated DMA request variants +3/-3

Move TIM1 CH1–CH3 outputs to dedicated DMA request variants

• Changes TIM1 CH3/CH2/CH1 dmavar from 0 to 1 for S2–S4 outputs to avoid combined advanced-timer DMA request usage. Prevents sibling-channel compare events from corrupting DSHOT DMA transfers.

src/main/target/PIXRACER/target.c

target.cMove TIM8 CH1–CH3 outputs to dedicated DMA request variants +3/-3

Move TIM8 CH1–CH3 outputs to dedicated DMA request variants

• Updates TIM8 CH1/CH2/CH3 dmavar from 0 to 1 to select dedicated DMA request options. Avoids combined CH1/CH2/CH3 request line interference during DMA-driven output.

src/main/target/REVO/target.c

target.cMove TIM8 CH3 and CH2N outputs to dedicated DMA request variants +2/-2

Move TIM8 CH3 and CH2N outputs to dedicated DMA request variants

• Changes TIM8 CH3 (S5) and TIM8 CH2N (S7) dmavar from 0 to 1 to avoid combined advanced-timer DMA request usage. Improves reliability for DMA-driven motor/servo outputs.

src/main/target/SPEEDYBEEF405WING/target.c

target.cMove TIM8 CH3 and CH2N outputs to dedicated DMA request variants +2/-2

Move TIM8 CH3 and CH2N outputs to dedicated DMA request variants

• Updates TIM8 CH3 (S5) and TIM8 CH2N (S7) dmavar from 0 to 1 to select dedicated DMA request mappings. Reduces risk of silent DSHOT corruption due to shared request lines.

src/main/target/SPEEDYBEEF405WINGV2/target.c

target.cCorrect TIM8 CH1–CH2 dmavar selection for F7 DMA-map ordering +2/-2

Correct TIM8 CH1–CH2 dmavar selection for F7 DMA-map ordering

• Changes TIM8 CH1 and CH2 dmavar from 1 to 0 to select the dedicated DMA request option on STM32F7, where the header table orders dedicated/combined variants oppositely from F4. Prevents inadvertently choosing the combined CH1/CH2/CH3 request line by F4 convention.

src/main/target/TMOTORF7/target.c

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RAM / Flash usage vs. base branch — commit 1c4418e

Target	Flash Δ	RAM Δ
MATEKF405	±0 B (±0.00%)	±0 B (±0.00%)
MATEKF722	±0 B (±0.00%)	±0 B (±0.00%)
MATEKF765	±0 B (±0.00%)	±0 B (±0.00%)
MATEKH743	±0 B (±0.00%)	±0 B (±0.00%)

See RAM/flash optimization guide for techniques to reduce usage.

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Test firmware build ready — commit 1c4418e

Download firmware for PR #11815

245 targets built. Find your board's .hex file by name on that page (e.g. MATEKF405SE.hex). Files are individually downloadable — no GitHub login required.

Development build for testing only. Use Full Chip Erase when flashing.