Skip to content

simd(riscv64): 6x8 RVV GEMM micro-kernel - #36

Merged
tannevaled merged 1 commit into
mainfrom
simd/riscv64-gemm
Oct 8, 2026
Merged

tannevaled merged 1 commit into
mainfrom
simd/riscv64-gemm

Conversation

@tannevaled

Copy link
Copy Markdown
Contributor

What

gemmMicro6x8RVV, generated by go-asmgen (riscv64/gen.go), with no WORDs. NR is fixed by the packing, while VLEN varies between RISC-V cores. Since V guarantees VLEN ≥ 128, a group of four registers (LMUL=4) always holds 8 float64, so VSETIVLI $8, E64, M4 gives vl = 8 on every core. The tile uses six accumulator groups. Each step loads the B row once and fuses each A value in with vfmacc.vf (Go: VFMACCVF Vb, Fa, Vacc computes Vacc += Fa·Vb, decoded from Go's testdata).

gemm_riscv64.go: MR=6, NR=8, gated on useRVV. Without V, the same tile runs in Go (gemmMicroGo). gemm_generic.go now excludes riscv64.

Tests on real hardware

  • cfarm95 (SpacemiT X60, V): GEMM, MatMul, fence and stress tests all pass, plus the full root and kernels suites.
  • cfarm94 (SiFive U74, no V): the same binary takes the Go 6×8 tile and passes.
  • Sabotage, caught on cfarm95: dropping the FMA of tile row 5 (MatMul m=50 k=70 n=90 [450]: 0 != -94).
  • Coverage 100% with -race; go vet on 7 architectures.

Measured (X60, one core) with the fleet's Go tools, no ad-hoc scripts

hostload -pick 1 (go-fleettools/fleettools#60) picked an idle CPU on a host that was 64% busy with others' niced jobs. benchstat compared 8 interleaved runs each against v0.7.0, with p = 0.000 everywhere:

64² 128² 256² 512² 1024²
MatMul time −31% −32% −45% −43% −44% (1.79 s → 1.00 s)

Inner −44%, small rectangular products −22% to −38%, geomean −36%. Absolute speed is about 2.1 GFLOP/s per core. With VLEN = 256, LMUL=4 uses half of each group; that is the price of one tile portable to every VLEN, and it is documented.

Version: v0.7.1 (performance, no API change).

🤖 Generated with Claude Code

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
@tannevaled
tannevaled merged commit c71adc5 into main Oct 8, 2026
12 checks passed
@tannevaled
tannevaled deleted the simd/riscv64-gemm branch October 8, 2026 11:51
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant