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simd(riscv64): 6x8 RVV GEMM micro-kernel - #36
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Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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What
gemmMicro6x8RVV, generated by go-asmgen (riscv64/gen.go), with no WORDs. NR is fixed by the packing, while VLEN varies between RISC-V cores. Since V guarantees VLEN ≥ 128, a group of four registers (LMUL=4) always holds 8 float64, soVSETIVLI $8, E64, M4gives vl = 8 on every core. The tile uses six accumulator groups. Each step loads the B row once and fuses each A value in withvfmacc.vf(Go:VFMACCVF Vb, Fa, Vacccomputes Vacc += Fa·Vb, decoded from Go's testdata).gemm_riscv64.go: MR=6, NR=8, gated onuseRVV. Without V, the same tile runs in Go (gemmMicroGo).gemm_generic.gonow excludes riscv64.Tests on real hardware
MatMul m=50 k=70 n=90 [450]: 0 != -94).-race;go veton 7 architectures.Measured (X60, one core) with the fleet's Go tools, no ad-hoc scripts
hostload -pick 1(go-fleettools/fleettools#60) picked an idle CPU on a host that was 64% busy with others' niced jobs.benchstatcompared 8 interleaved runs each against v0.7.0, with p = 0.000 everywhere:Inner −44%, small rectangular products −22% to −38%, geomean −36%. Absolute speed is about 2.1 GFLOP/s per core. With VLEN = 256, LMUL=4 uses half of each group; that is the price of one tile portable to every VLEN, and it is documented.
Version: v0.7.1 (performance, no API change).
🤖 Generated with Claude Code