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drivers: pinctrl: microchip: update pinctrl driver for Port G1
Updates G1 pinctrl driver Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
1 parent d90bd3a commit 3c79fb3

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6 files changed

+174
-3
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6 files changed

+174
-3
lines changed

‎drivers/pinctrl/Kconfig.mchp‎

Lines changed: 26 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,34 @@
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# Copyright (c) 2025 Microchip Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
33

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config PINCTRL_MCHP_COMMON
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bool "Microchip pin controller"
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help
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Common options for Microchip pinctrl drivers.
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config PINCTRL_MCHP_PORT_G1
5-
bool "Microchip PORT G1 pin controller driver"
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bool
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default y
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depends on DT_HAS_MICROCHIP_PORT_G1_PINCTRL_ENABLED
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select PINCTRL_MCHP_COMMON
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help
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This option enables PINCTRL driver for group (g1) of PORT peripherals.
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if PINCTRL_MCHP_COMMON
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config PIN_OPEN_DRAIN
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bool "Support for open-drain option"
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help
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This option enables Open drain configuration for the pin.
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config PIN_SLEW_RATE
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bool "Support for slew-rate control"
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help
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This option enables Slew rate for the pin.
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config PIN_DRIVE_STRENGTH
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bool "Support for drive strength"
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help
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This option enables Drive strength for the pin.
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endif # PINCTRL_MCHP_COMMON

‎drivers/pinctrl/pinctrl_mchp_port_g1.c‎

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Original file line numberDiff line numberDiff line change
@@ -42,6 +42,9 @@ static const uint32_t mchp_port_addrs[] = {
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MCHP_PORT_ADDR_OR_NONE(portb)
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MCHP_PORT_ADDR_OR_NONE(portc)
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MCHP_PORT_ADDR_OR_NONE(portd)
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MCHP_PORT_ADDR_OR_NONE(porte)
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MCHP_PORT_ADDR_OR_NONE(portf)
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MCHP_PORT_ADDR_OR_NONE(portg)
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};
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/* clang-format on */
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@@ -130,13 +133,35 @@ static void pinctrl_set_flags(const pinctrl_soc_pin_t *pin)
130133
} else {
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pRegister->PORT_DIR &= ~(1 << pin_num);
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}
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#ifdef CONFIG_PIN_OPEN_DRAIN
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if ((pin->pinflag & MCHP_PINCTRL_OPENDRAIN) != 0) {
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pRegister->PORT_PINCFG[pin_num] |= PORT_PINCFG_ODRAIN(1);
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} else {
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pRegister->PORT_PINCFG[pin_num] &= ~PORT_PINCFG_ODRAIN(1);
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}
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#endif /* CONFIG_PIN_OPEN_DRAIN */
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#ifdef CONFIG_PIN_SLEW_RATE
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uint8_t slewrate_val = 0U;
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if ((pin->pinflag & MCHP_PINCTRL_SLEWRATE) != 0) {
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/* Extract Slew Rate Value from pinflag and update the register */
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slewrate_val =
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(pin->pinflag & MCHP_PINCTRL_SLEWRATE) >> MCHP_PINCTRL_SLEWRATE_POS;
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}
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pRegister->PORT_PINCFG[pin_num] =
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(pRegister->PORT_PINCFG[pin_num] & ~PORT_PINCFG_SLEWLIM_Msk) |
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PORT_PINCFG_SLEWLIM(slewrate_val);
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#endif /* CONFIG_PIN_SLEW_RATE */
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#ifdef CONFIG_PIN_DRIVE_STRENGTH
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/* if drive strength is enabled, set the corresponding bit in PORT_PINCFG reg */
135159
if ((pin->pinflag & MCHP_PINCTRL_DRIVESTRENGTH) != 0) {
136160
pRegister->PORT_PINCFG[pin_num] |= PORT_PINCFG_DRVSTR(1);
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} else {
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pRegister->PORT_PINCFG[pin_num] &= ~PORT_PINCFG_DRVSTR(1);
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}
164+
#endif /* CONFIG_PIN_DRIVE_STRENGTH */
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}
141166
}
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‎soc/microchip/pic32c/pic32cz_ca/CMakeLists.txt‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
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# Copyright (c) 2025 Microchip Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
33

4-
zephyr_include_directories(${SOC_SERIES})
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add_subdirectory(common)
55

6-
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
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zephyr_include_directories(${SOC_SERIES})

‎soc/microchip/pic32c/pic32cz_ca/Kconfig‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,3 +16,5 @@ config SOC_FAMILY_MICROCHIP_PIC32CZ_CA
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select HAS_SWO
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select XIP
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select HAS_POWEROFF
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select PIN_OPEN_DRAIN if PINCTRL
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select PIN_SLEW_RATE if PINCTRL

‎soc/microchip/pic32c/pic32cz_ca/common/CMakeLists.txt‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
# Copyright (c) 2025 Microchip Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(.)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

‎soc/microchip/pic32c/pic32cz_ca/common/pinctrl_soc.h‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,113 @@
1+
/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
5+
*/
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#ifndef ZEPHYR_SOC_MICROCHIP_PIC32C_PIC32CZ_CA_COMMON_PINCTRL_SOC_H
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#define ZEPHYR_SOC_MICROCHIP_PIC32C_PIC32CZ_CA_COMMON_PINCTRL_SOC_H
9+
10+
#include <zephyr/devicetree.h>
11+
#include <zephyr/types.h>
12+
#include <dt-bindings/pic32c/pic32cz_ca/common/mchp_pinctrl_pinmux_pic32c.h>
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#ifdef __cplusplus
15+
extern "C" {
16+
#endif
17+
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/** @cond INTERNAL_HIDDEN */
19+
20+
/**
21+
* @brief Structure representing the pin control settings for a SOC pin.
22+
*
23+
* This structure is used to define the pinmux and pin configuration settings
24+
* for a specific pin on the SOC. It includes information about the port, pin,
25+
* function, bias, drive, and other configuration options.
26+
*/
27+
typedef struct pinctrl_soc_pin {
28+
/** Pinmux settings (port, pin and function). */
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uint16_t pinmux;
30+
/** Pin configuration (bias, drive etc). */
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uint16_t pinflag;
32+
} pinctrl_soc_pin_t;
33+
34+
/**
35+
* @brief Utility macro to initialize pinmux field.
36+
*
37+
* @param node_id Node identifier.
38+
* @param prop Property name.
39+
* @param idx Property entry index.
40+
*/
41+
#define Z_PINCTRL_MCHP_PINMUX_INIT(node_id, prop, idx) DT_PROP_BY_IDX(node_id, prop, idx)
42+
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/**
44+
* @brief Utility macro to initialize each pin flag.
45+
*
46+
* @param node_id Node identifier.
47+
* @param prop Property name.
48+
* @param idx Property entry index.
49+
*/
50+
#define Z_PINCTRL_MCHP_PINFLAG_INIT(node_id, prop, idx) \
51+
((DT_PROP(node_id, bias_pull_up) << MCHP_PINCTRL_PULLUP_POS) | \
52+
(DT_PROP(node_id, bias_pull_down) << MCHP_PINCTRL_PULLDOWN_POS) | \
53+
(DT_PROP(node_id, input_enable) << MCHP_PINCTRL_INPUTENABLE_POS) | \
54+
(DT_PROP(node_id, output_enable) << MCHP_PINCTRL_OUTPUTENABLE_POS) | \
55+
(DT_PROP(node_id, drive_open_drain) << MCHP_PINCTRL_OPENDRAIN_POS) | \
56+
(DT_ENUM_IDX(node_id, slew_rate) << MCHP_PINCTRL_SLEWRATE_POS)),
57+
58+
/**
59+
* @brief Utility macro to initialize each pin.
60+
*
61+
* @param node_id Node identifier.
62+
* @param prop Property name.
63+
* @param idx Property entry index.
64+
*/
65+
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
66+
{.pinmux = Z_PINCTRL_MCHP_PINMUX_INIT(node_id, prop, idx), \
67+
.pinflag = Z_PINCTRL_MCHP_PINFLAG_INIT(node_id, prop, idx)},
68+
69+
/**
70+
* @brief Utility macro to initialize state pins contained in a given property.
71+
*
72+
* @param node_id Node identifier.
73+
* @param prop Property name describing state pins.
74+
*/
75+
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
76+
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
77+
Z_PINCTRL_STATE_PIN_INIT)}
78+
79+
/** @endcond */
80+
81+
/**
82+
* @brief Pin flags/attributes
83+
* @anchor MCHP_PINFLAGS
84+
*
85+
* @{
86+
*/
87+
88+
#define MCHP_PINCTRL_FLAGS_DEFAULT (0U)
89+
#define MCHP_PINCTRL_FLAGS_POS (0U)
90+
#define MCHP_PINCTRL_FLAGS_MASK (0x3F << MCHP_PINCTRL_FLAGS_POS)
91+
#define MCHP_PINCTRL_FLAG_MASK (1U)
92+
#define MCHP_PINCTRL_PULLUP_POS (MCHP_PINCTRL_FLAGS_POS)
93+
#define MCHP_PINCTRL_PULLUP (1U << MCHP_PINCTRL_PULLUP_POS)
94+
#define MCHP_PINCTRL_PULLDOWN_POS (MCHP_PINCTRL_PULLUP_POS + 1U)
95+
#define MCHP_PINCTRL_PULLDOWN (1U << MCHP_PINCTRL_PULLDOWN_POS)
96+
#define MCHP_PINCTRL_OPENDRAIN_POS (MCHP_PINCTRL_PULLDOWN_POS + 1U)
97+
#define MCHP_PINCTRL_OPENDRAIN (1U << MCHP_PINCTRL_OPENDRAIN_POS)
98+
#define MCHP_PINCTRL_INPUTENABLE_POS (MCHP_PINCTRL_OPENDRAIN_POS + 1U)
99+
#define MCHP_PINCTRL_INPUTENABLE (1U << MCHP_PINCTRL_INPUTENABLE_POS)
100+
#define MCHP_PINCTRL_OUTPUTENABLE_POS (MCHP_PINCTRL_INPUTENABLE_POS + 1U)
101+
#define MCHP_PINCTRL_OUTPUTENABLE (1U << MCHP_PINCTRL_OUTPUTENABLE_POS)
102+
#define MCHP_PINCTRL_DRIVESTRENGTH_POS (MCHP_PINCTRL_OUTPUTENABLE_POS + 1U)
103+
#define MCHP_PINCTRL_DRIVESTRENGTH (1U << MCHP_PINCTRL_DRIVESTRENGTH_POS)
104+
#define MCHP_PINCTRL_SLEWRATE_POS (MCHP_PINCTRL_DRIVESTRENGTH_POS + 1U)
105+
#define MCHP_PINCTRL_SLEWRATE (3U << MCHP_PINCTRL_SLEWRATE_POS)
106+
107+
/** @} */
108+
109+
#ifdef __cplusplus
110+
}
111+
#endif
112+
113+
#endif /*ZEPHYR_SOC_MICROCHIP_PIC32C_PIC32CZ_CA_COMMON_PINCTRL_SOC_H*/

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