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AzharMCHPnashif
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dts: arm: microchip: pic32cz_ca: Add pinctrl nodes
Adds the pinctrl node and encapsulates the port nodes within the pinctrl node for pic32cz ca series of socs, and updates the binding file Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
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‎dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca.dtsi‎

Lines changed: 38 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -36,40 +36,47 @@
3636
compatible = "mmio-sram";
3737
};
3838

39-
porta: gpio@44840000 {
40-
status = "disabled";
41-
compatible = "microchip,port-g1-gpio";
42-
reg = <0x44840000 0x80>;
43-
gpio-controller;
44-
#gpio-cells = <2>;
45-
#microchip,pin-cells = <2>;
46-
};
39+
pinctrl: pinctrl@44840000 {
40+
compatible = "microchip,port-g1-pinctrl";
41+
#address-cells = <1>;
42+
#size-cells = <1>;
43+
ranges = <0x44840000 0x44840000 0x380>;
4744

48-
portb: gpio@44840080 {
49-
status = "disabled";
50-
compatible = "microchip,port-g1-gpio";
51-
reg = <0x44840080 0x80>;
52-
gpio-controller;
53-
#gpio-cells = <2>;
54-
#microchip,pin-cells = <2>;
55-
};
45+
porta: gpio@44840000 {
46+
compatible = "microchip,port-g1-gpio";
47+
reg = <0x44840000 0x80>;
48+
gpio-controller;
49+
#gpio-cells = <2>;
50+
#microchip,pin-cells = <2>;
51+
status = "disabled";
52+
};
5653

57-
portc: gpio@44840100 {
58-
status = "disabled";
59-
compatible = "microchip,port-g1-gpio";
60-
reg = <0x44840100 0x80>;
61-
gpio-controller;
62-
#gpio-cells = <2>;
63-
#microchip,pin-cells = <2>;
64-
};
54+
portb: gpio@44840080 {
55+
compatible = "microchip,port-g1-gpio";
56+
reg = <0x44840080 0x80>;
57+
gpio-controller;
58+
#gpio-cells = <2>;
59+
#microchip,pin-cells = <2>;
60+
status = "disabled";
61+
};
6562

66-
portd: gpio@44840180 {
67-
status = "disabled";
68-
compatible = "microchip,port-g1-gpio";
69-
reg = <0x44840180 0x80>;
70-
gpio-controller;
71-
#gpio-cells = <2>;
72-
#microchip,pin-cells = <2>;
63+
portc: gpio@44840100 {
64+
compatible = "microchip,port-g1-gpio";
65+
reg = <0x44840100 0x80>;
66+
gpio-controller;
67+
#gpio-cells = <2>;
68+
#microchip,pin-cells = <2>;
69+
status = "disabled";
70+
};
71+
72+
portd: gpio@44840180 {
73+
compatible = "microchip,port-g1-gpio";
74+
reg = <0x44840180 0x80>;
75+
gpio-controller;
76+
#gpio-cells = <2>;
77+
#microchip,pin-cells = <2>;
78+
status = "disabled";
79+
};
7380
};
7481
};
7582
};

‎dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca_176.dtsi‎

Lines changed: 24 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -6,33 +6,31 @@
66

77
#include <microchip/pic32c/pic32cz_ca/common/pic32cz_ca.dtsi>
88

9-
/ {
10-
soc {
11-
porte: gpio@44840200 {
12-
status = "disabled";
13-
compatible = "microchip,port-g1-gpio";
14-
reg = <0x44840200 0x80>;
15-
gpio-controller;
16-
#gpio-cells = <2>;
17-
#microchip,pin-cells = <2>;
18-
};
9+
&pinctrl {
10+
porte: gpio@44840200 {
11+
compatible = "microchip,port-g1-gpio";
12+
reg = <0x44840200 0x80>;
13+
gpio-controller;
14+
#gpio-cells = <2>;
15+
#microchip,pin-cells = <2>;
16+
status = "disabled";
17+
};
1918

20-
portf: gpio@44840280 {
21-
status = "disabled";
22-
compatible = "microchip,port-g1-gpio";
23-
reg = <0x44840280 0x80>;
24-
gpio-controller;
25-
#gpio-cells = <2>;
26-
#microchip,pin-cells = <2>;
27-
};
19+
portf: gpio@44840280 {
20+
compatible = "microchip,port-g1-gpio";
21+
reg = <0x44840280 0x80>;
22+
gpio-controller;
23+
#gpio-cells = <2>;
24+
#microchip,pin-cells = <2>;
25+
status = "disabled";
26+
};
2827

29-
portg: gpio@44840300 {
30-
status = "disabled";
31-
compatible = "microchip,port-g1-gpio";
32-
reg = <0x44840300 0x80>;
33-
gpio-controller;
34-
#gpio-cells = <2>;
35-
#microchip,pin-cells = <2>;
36-
};
28+
portg: gpio@44840300 {
29+
compatible = "microchip,port-g1-gpio";
30+
reg = <0x44840300 0x80>;
31+
gpio-controller;
32+
#gpio-cells = <2>;
33+
#microchip,pin-cells = <2>;
34+
status = "disabled";
3735
};
3836
};

‎dts/arm/microchip/pic32c/pic32cz_ca/common/pic32cz_ca_208.dtsi‎

Lines changed: 24 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -6,33 +6,31 @@
66

77
#include <microchip/pic32c/pic32cz_ca/common/pic32cz_ca.dtsi>
88

9-
/ {
10-
soc {
11-
porte: gpio@44840200 {
12-
status = "disabled";
13-
compatible = "microchip,port-g1-gpio";
14-
reg = <0x44840200 0x80>;
15-
gpio-controller;
16-
#gpio-cells = <2>;
17-
#microchip,pin-cells = <2>;
18-
};
9+
&pinctrl {
10+
porte: gpio@44840200 {
11+
compatible = "microchip,port-g1-gpio";
12+
reg = <0x44840200 0x80>;
13+
gpio-controller;
14+
#gpio-cells = <2>;
15+
#microchip,pin-cells = <2>;
16+
status = "disabled";
17+
};
1918

20-
portf: gpio@44840280 {
21-
status = "disabled";
22-
compatible = "microchip,port-g1-gpio";
23-
reg = <0x44840280 0x80>;
24-
gpio-controller;
25-
#gpio-cells = <2>;
26-
#microchip,pin-cells = <2>;
27-
};
19+
portf: gpio@44840280 {
20+
compatible = "microchip,port-g1-gpio";
21+
reg = <0x44840280 0x80>;
22+
gpio-controller;
23+
#gpio-cells = <2>;
24+
#microchip,pin-cells = <2>;
25+
status = "disabled";
26+
};
2827

29-
portg: gpio@44840300 {
30-
status = "disabled";
31-
compatible = "microchip,port-g1-gpio";
32-
reg = <0x44840300 0x80>;
33-
gpio-controller;
34-
#gpio-cells = <2>;
35-
#microchip,pin-cells = <2>;
36-
};
28+
portg: gpio@44840300 {
29+
compatible = "microchip,port-g1-gpio";
30+
reg = <0x44840300 0x80>;
31+
gpio-controller;
32+
#gpio-cells = <2>;
33+
#microchip,pin-cells = <2>;
34+
status = "disabled";
3735
};
3836
};

‎dts/bindings/pinctrl/microchip,port-g1-pinctrl.yaml‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@ description: |
1414
Group g1 PORT PINCTRL driver supports following hardware peripherals:
1515
- module name="PORT" id="U2210" version="2.2.0"
1616
- module name="PORT" id="U2210" version="3.1.0"
17+
- module name="PORT" id="03720" version="4a0"
1718
1819
The node has the 'pinctrl' node label set in your SoC's devicetree, so you can
1920
modify it like this:
@@ -67,6 +68,12 @@ description: |
6768
- drive-strength: Increase sink current.
6869
- input-enable: Enable input on pin.
6970
- output-enable: Enable output on a pin without actively driving it.
71+
- drive-open-drain: Enable open-drain for the pin.
72+
- slew-rate: Provide slew rate for the pin (Choose from the options below).
73+
- "fast"
74+
- "slow4"
75+
- "slow8"
76+
- "slow12"
7077
7178
To link pin configurations with a device, use a pinctrl-N property for some
7279
number N, like this example you could place in your board's DTS file:
@@ -105,6 +112,7 @@ child-binding:
105112
- drive-strength
106113
- input-enable
107114
- output-enable
115+
- drive-open-drain
108116

109117
properties:
110118
pinmux:
@@ -125,3 +133,19 @@ child-binding:
125133
configured as an output.
126134
0: Pin drive strength is set to normal drive strength.
127135
1: Pin drive strength is set to stronger drive strength.
136+
slew-rate:
137+
default: "fast"
138+
type: string
139+
enum:
140+
- "fast"
141+
- "slow4"
142+
- "slow8"
143+
- "slow12"
144+
description: |
145+
Pin speed. The default value of slew-rate is the SoC power-on-reset
146+
value. Slew rate control can be used to improve signal integrity
147+
for high-speed signals
148+
fast: Slew rate control disabled (fast).
149+
slow4: Slew rate control enabled (4x slower).
150+
slow8: Slew rate control enabled (8x slower).
151+
slow12: Slew rate control enabled (12x slower).

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