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Bump Object Crate to 0.39.0 #348

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66e68fa
Bump Object Crate to 0.39.0
HaydnTrigg Apr 14, 2026
95dc589
Format split_meta.rs
HaydnTrigg Apr 15, 2026
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4 changes: 2 additions & 2 deletions Cargo.lock
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2 changes: 1 addition & 1 deletion objdiff-core/Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -132,7 +132,7 @@ itertools = { version = "0.14", default-features = false, features = ["use_alloc
log = { version = "0.4", default-features = false, optional = true }
memmap2 = { version = "0.9", optional = true }
num-traits = { version = "0.2", default-features = false, optional = true }
object = { version = "0.37", default-features = false, features = ["read_core", "elf", "coff"] }
object = { version = "0.39", default-features = false, features = ["read_core", "elf", "coff"] }
pbjson = { version = "0.8", default-features = false, optional = true }
prost = { version = "0.14", default-features = false, features = ["derive"], optional = true }
regex = { version = "1.12", default-features = false, features = [], optional = true }
Expand Down
12 changes: 6 additions & 6 deletions objdiff-core/src/arch/arm.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -352,17 +352,17 @@ impl Arch for ArchArm {
| elf::R_ARM_CALL
| elf::R_ARM_JUMP24 => {
let data = section_data[address..address + 4].try_into()?;
let addend = self.endianness.read_i32_bytes(data);
let addend = self.endianness.read_i32(data);
let imm24 = addend & 0xffffff;
(imm24 << 2) << 8 >> 8
}

// Thumb calls
elf::R_ARM_THM_PC22 | elf::R_ARM_THM_XPC22 => {
let data = section_data[address..address + 2].try_into()?;
let high = self.endianness.read_i16_bytes(data) as i32;
let high = self.endianness.read_i16(data) as i32;
let data = section_data[address + 2..address + 4].try_into()?;
let low = self.endianness.read_i16_bytes(data) as i32;
let low = self.endianness.read_i16(data) as i32;

let imm22 = ((high & 0x7ff) << 11) | (low & 0x7ff);
(imm22 << 1) << 9 >> 9
Expand All @@ -371,23 +371,23 @@ impl Arch for ArchArm {
// Thumb unconditional branch (B, 11-bit offset)
elf::R_ARM_THM_PC11 => {
let data = section_data[address..address + 2].try_into()?;
let insn = self.endianness.read_u16_bytes(data) as i32;
let insn = self.endianness.read_u16(data) as i32;
let imm11 = insn & 0x7ff;
(imm11 << 1) << 20 >> 20
}

// Thumb conditional branch (B<cond>, 8-bit offset)
elf::R_ARM_THM_PC9 => {
let data = section_data[address..address + 2].try_into()?;
let insn = self.endianness.read_u16_bytes(data) as i32;
let insn = self.endianness.read_u16(data) as i32;
let imm8 = insn & 0xff;
(imm8 << 1) << 23 >> 23
}

// Data
elf::R_ARM_ABS32 => {
let data = section_data[address..address + 4].try_into()?;
self.endianness.read_i32_bytes(data)
self.endianness.read_i32(data)
}

flags => bail!("Unsupported ARM implicit relocation {flags:?}"),
Expand Down
14 changes: 7 additions & 7 deletions objdiff-core/src/arch/mips.rs
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Expand Up @@ -77,7 +77,7 @@ impl ArchMips {
.and_then(|section| section.data().ok())
.and_then(|data| data.get(0x14..0x18))
.and_then(|s| s.try_into().ok())
.map(|bytes| endianness.read_i32_bytes(bytes))
.map(|bytes| endianness.read_i32(bytes))
.unwrap_or(0);

// Parse all relocations to pair R_MIPS_HI16 and R_MIPS_LO16. Since the instructions only
Expand All @@ -98,13 +98,13 @@ impl ArchMips {
match reloc.flags() {
object::RelocationFlags::Elf { r_type: elf::R_MIPS_HI16 } => {
let code = data[addr as usize..addr as usize + 4].try_into()?;
let addend = ((endianness.read_u32_bytes(code) & 0x0000FFFF) << 16) as i32;
let addend = ((endianness.read_u32(code) & 0x0000FFFF) << 16) as i32;
last_hi = Some(addr);
last_hi_addend = addend;
}
object::RelocationFlags::Elf { r_type: elf::R_MIPS_LO16 } => {
let code = data[addr as usize..addr as usize + 4].try_into()?;
let addend = (endianness.read_u32_bytes(code) & 0x0000FFFF) as i16 as i32;
let addend = (endianness.read_u32(code) & 0x0000FFFF) as i16 as i32;
let full_addend = (last_hi_addend + addend) as i64;
if let Some(hi_addr) = last_hi.take() {
addends.insert(hi_addr, full_addend);
Expand Down Expand Up @@ -197,7 +197,7 @@ impl ArchMips {
diff_config: &DiffObjConfig,
) -> Result<rabbitizer::Instruction> {
Ok(rabbitizer::Instruction::new(
self.endianness.read_u32_bytes(code.try_into()?),
self.endianness.read_u32(code.try_into()?),
Vram::new(ins_ref.address as u32),
self.instruction_flags(diff_config),
))
Expand All @@ -217,7 +217,7 @@ impl Arch for ArchMips {
let mut ops = Vec::<InstructionRef>::with_capacity(code.len() / 4);
let mut cur_addr = address as u32;
for chunk in code.chunks_exact(4) {
let code = self.endianness.read_u32_bytes(chunk.try_into()?);
let code = self.endianness.read_u32(chunk.try_into()?);
let instruction =
rabbitizer::Instruction::new(code, Vram::new(cur_addr), instruction_flags);
let opcode = instruction.opcode() as u16;
Expand Down Expand Up @@ -269,7 +269,7 @@ impl Arch for ArchMips {
let data = section.data()?;
let code = self
.endianness
.read_u32_bytes(data[address as usize..address as usize + 4].try_into()?);
.read_u32(data[address as usize..address as usize + 4].try_into()?);
let addend = match r_type {
elf::R_MIPS_32 => code as i64,
elf::R_MIPS_26 => ((code & 0x03FFFFFF) << 2) as i64,
Expand Down Expand Up @@ -366,7 +366,7 @@ impl Arch for ArchMips {
&& new_address >= symbol.address + 4
&& let Some(data) = section.data_range(new_address - 4, 4)
&& let instruction = rabbitizer::Instruction::new(
self.endianness.read_u32_bytes(data.try_into().unwrap()),
self.endianness.read_u32(data.try_into().unwrap()),
Vram::new((new_address - 4) as u32),
self.default_instruction_flags(),
)
Expand Down
6 changes: 3 additions & 3 deletions objdiff-core/src/arch/mod.rs
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Expand Up @@ -125,23 +125,23 @@ impl DataType {
}
}
DataType::Int16 => {
let i = endian.read_i16_bytes(bytes.try_into().unwrap());
let i = endian.read_i16(bytes.try_into().unwrap());
strs.push((format!("{i:#x}"), None, None));

if i < 0 {
strs.push((format!("{:#x}", ReallySigned(i)), None, None));
}
}
DataType::Int32 => {
let i = endian.read_i32_bytes(bytes.try_into().unwrap());
let i = endian.read_i32(bytes.try_into().unwrap());
strs.push((format!("{i:#x}"), None, None));

if i < 0 {
strs.push((format!("{:#x}", ReallySigned(i)), None, None));
}
}
DataType::Int64 => {
let i = endian.read_i64_bytes(bytes.try_into().unwrap());
let i = endian.read_i64(bytes.try_into().unwrap());
strs.push((format!("{i:#x}"), None, None));

if i < 0 {
Expand Down
10 changes: 5 additions & 5 deletions objdiff-core/src/arch/x86.rs
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Expand Up @@ -193,8 +193,8 @@ impl Arch for ArchX86 {
if resolved.ins_ref.opcode == OPCODE_DATA {
let (mnemonic, imm) = match resolved.ins_ref.size {
1 => (".byte", resolved.code[0] as u64),
2 => (".word", self.endianness.read_u16_bytes(resolved.code.try_into()?) as u64),
4 => (".dword", self.endianness.read_u32_bytes(resolved.code.try_into()?) as u64),
2 => (".word", self.endianness.read_u16(resolved.code.try_into()?) as u64),
4 => (".dword", self.endianness.read_u32(resolved.code.try_into()?) as u64),
_ => bail!("Unsupported x86 inline data size {}", resolved.ins_ref.size),
};
cb(InstructionPart::opcode(mnemonic, OPCODE_DATA))?;
Expand Down Expand Up @@ -288,7 +288,7 @@ impl Arch for ArchX86 {
} => {
let data =
section.data()?[address as usize..address as usize + 4].try_into()?;
self.endianness.read_i32_bytes(data) as i64
self.endianness.read_i32(data) as i64
}
flags => bail!("Unsupported x86 implicit relocation {flags:?}"),
},
Expand All @@ -299,13 +299,13 @@ impl Arch for ArchX86 {
| object::RelocationFlags::Elf { r_type: elf::R_X86_64_32 | elf::R_X86_64_PC32 } => {
let data =
section.data()?[address as usize..address as usize + 4].try_into()?;
self.endianness.read_i32_bytes(data) as i64
self.endianness.read_i32(data) as i64
}
object::RelocationFlags::Coff { typ: pe::IMAGE_REL_AMD64_ADDR64 }
| object::RelocationFlags::Elf { r_type: elf::R_X86_64_64 } => {
let data =
section.data()?[address as usize..address as usize + 8].try_into()?;
self.endianness.read_i64_bytes(data)
self.endianness.read_i64(data)
}
flags => bail!("Unsupported x86-64 implicit relocation {flags:?}"),
},
Expand Down
19 changes: 9 additions & 10 deletions objdiff-core/src/obj/split_meta.rs
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Expand Up @@ -53,22 +53,21 @@ impl SplitMeta {
result.module_name = Some(string);
}
NT_SPLIT_MODULE_ID => {
result.module_id = Some(e.read_u32_bytes(
result.module_id = Some(e.read_u32(
note.desc.try_into().map_err(|_| anyhow!("Invalid module ID size"))?,
));
}
NT_SPLIT_VIRTUAL_ADDRESSES => {
let vec = if is_64 {
let mut vec = vec![0u64; note.desc.len() / 8];
for (i, v) in vec.iter_mut().enumerate() {
*v =
e.read_u64_bytes(note.desc[i * 8..(i + 1) * 8].try_into().unwrap());
*v = e.read_u64(note.desc[i * 8..(i + 1) * 8].try_into().unwrap());
}
vec
} else {
let mut vec = vec![0u64; note.desc.len() / 4];
for (i, v) in vec.iter_mut().enumerate() {
*v = e.read_u32_bytes(note.desc[i * 4..(i + 1) * 4].try_into().unwrap())
*v = e.read_u32(note.desc[i * 4..(i + 1) * 4].try_into().unwrap())
as u64;
}
vec
Expand Down Expand Up @@ -101,19 +100,19 @@ impl SplitMeta {
}
if let Some(module_id) = self.module_id {
write_note_header(writer, e, NT_SPLIT_MODULE_ID, 4)?;
writer.write_all(&e.write_u32_bytes(module_id))?;
writer.write_all(&e.write_u32(module_id))?;
}
if let Some(virtual_addresses) = &self.virtual_addresses {
let count = virtual_addresses.len();
let size = if is_64 { count * 8 } else { count * 4 };
write_note_header(writer, e, NT_SPLIT_VIRTUAL_ADDRESSES, size)?;
if is_64 {
for &addr in virtual_addresses {
writer.write_all(&e.write_u64_bytes(addr))?;
writer.write_all(&e.write_u64(addr))?;
}
} else {
for &addr in virtual_addresses {
writer.write_all(&e.write_u32_bytes(addr as u32))?;
writer.write_all(&e.write_u32(addr as u32))?;
}
}
}
Expand Down Expand Up @@ -208,9 +207,9 @@ where
E: Endian,
W: std::io::Write + ?Sized,
{
writer.write_all(&e.write_u32_bytes(ELF_NOTE_SPLIT.len() as u32 + 1))?; // Name Size
writer.write_all(&e.write_u32_bytes(desc_len as u32))?; // Desc Size
writer.write_all(&e.write_u32_bytes(kind))?; // Type
writer.write_all(&e.write_u32(ELF_NOTE_SPLIT.len() as u32 + 1))?; // Name Size
writer.write_all(&e.write_u32(desc_len as u32))?; // Desc Size
writer.write_all(&e.write_u32(kind))?; // Type
writer.write_all(ELF_NOTE_SPLIT)?; // Name
writer.write_all(&[0; 1])?; // Null terminator
align_data_to_4(writer, ELF_NOTE_SPLIT.len() + 1)?;
Expand Down
4 changes: 2 additions & 2 deletions objdiff-core/src/util.rs
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Expand Up @@ -28,14 +28,14 @@ impl<N: PrimInt> fmt::UpperHex for ReallySigned<N> {

pub fn read_u32(obj_file: &object::File, reader: &mut &[u8]) -> Result<u32> {
ensure!(reader.len() >= 4, "Not enough bytes to read u32");
let value = u32::from_ne_bytes(reader[..4].try_into()?);
let value = reader[..4].try_into()?;
*reader = &reader[4..];
Ok(obj_file.endianness().read_u32(value))
}

pub fn read_u16(obj_file: &object::File, reader: &mut &[u8]) -> Result<u16> {
ensure!(reader.len() >= 2, "Not enough bytes to read u16");
let value = u16::from_ne_bytes(reader[..2].try_into()?);
let value = reader[..2].try_into()?;
*reader = &reader[2..];
Ok(obj_file.endianness().read_u16(value))
}
Expand Down
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