Share DeepNVMe pinned-tensor manager and route swap buffers through I/O handles - #8212
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sfc-gh-truwase wants to merge 2 commits into
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Share DeepNVMe pinned-tensor manager and route swap buffers through I/O handles#8212sfc-gh-truwase wants to merge 2 commits into
sfc-gh-truwase wants to merge 2 commits into
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…/O handles DeepNVMe skips the bounce-buffer copy only when a buffer is torch-pinned or managed by the handle's pinned-tensor manager. That manager was per-handle and recognized only exact base pointers, so buffers allocated by one handle (or narrows/views of a shared pool submitted through a different read/write handle) were not recognized and always bounced. - C++: make deepspeed_pin_tensor_t a process-wide shared() singleton guarded by a mutex, and make is_managed range-based so slices/views of a locked buffer are recognized. Switch deepspeed_io_handle_t and cpu_op_desc_t to hold the manager via shared_ptr, and add handle.is_pinned() with aio/gds bindings. - Python: the swap subsystem now obtains pinned host memory via new_cpu_locked_tensor and queries pinned status via handle.is_pinned instead of the accelerator. SwapBufferManager/SwapBufferPool and the optimizer swappers take an aio_handle; optimizer-swapper subclasses create the handle before super().__init__ so it can be threaded through. - Add a focused nvme test for narrow recognition and cross-handle sharing. Signed-off-by: Olatunji Ruwase <tunji.ruwase@snowflake.com> Co-authored-by: Cursor <cursoragent@cursor.com>
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- handle.is_pinned() now returns is_pinned() || is_managed(), mirroring cpu_op_desc_t's direct-I/O eligibility check. Reporting only is_managed() misclassified torch-pinned destinations (e.g. ZeRO-3 fp16 flat CPU memory) as unpinned, needlessly forcing the swap-buffer path and risking pool exhaustion. - SwapBufferManager now releases its page-locked buffers via free_cpu_locked_tensor() on destruction. With the process-wide pinned-tensor manager, dropping a manager no longer reclaims its buffers, so repeatedly building NVMe swappers would otherwise accumulate locked memory. Signed-off-by: Olatunji Ruwase <tunji.ruwase@snowflake.com> Co-authored-by: Cursor <cursoragent@cursor.com>
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| const char* ptr = (char*)buffer.data_ptr(); | ||
| for (const auto& iter : _locked_tensors) { | ||
| const char* base = (char*)iter.first; | ||
| if (base <= ptr && ptr < base + iter.second) { return true; } |
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Do we need to check whether the end of buffer is smaller than iter.second? This could be stronger.
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Summary
DeepNVMe skips the bounce-buffer copy only when a buffer is torch-pinned or managed by the handle's pinned-tensor manager. That manager was per-handle and recognized only exact base pointers, so buffers allocated by one handle — or narrows/views of a shared pool submitted through a different read/write handle — were not recognized and always bounced.
This PR makes the pinned-tensor manager a process-wide shared instance with range-based recognition, and switches the swap subsystem to obtain pinned memory and query pinned status through its I/O handles.
Changes
deepspeed_pin_tensor_tis now a process-wideshared()singleton guarded by astd::mutex;is_managedis range-based so slices/views of a locked buffer are recognized.deepspeed_io_handle_tandcpu_op_desc_thold the manager viastd::shared_ptr.handle.is_pinned(buffer)with bindings inpy_ds_aio.cppandpy_ds_gds.cpp(GDS inherits the base).SwapBufferManager/SwapBufferPooland the optimizer swappers take anaio_handle; buffers are allocated vianew_cpu_locked_tensorand pinned status is queried viahandle.is_pinned.super().__init__so it can be threaded through.tests/unit/v1/nvme/test_pinned_manager.pycovers narrow/view recognition and cross-handle sharing.Test plan
pre-commit(yapf/flake8/clang-format/check-license) on all touched files.tests/unit/v1/nvme/test_pinned_manager.py— 3/3 pass (narrow recognition, cross-handle sharing, unmanaged buffer).tests/unit/v1/nvme/+tests/unit/utils/test_pin_memory.py+tests/unit/v1/accelerator/test_accelerator.py— 146 pass.tests/unit/runtime/zero/test_nvme_checkpointing.py): reproduces the pre-existing baseline exactly (no regression; the failing optimizer-on-NVMe configs fail identically onmaster).Made with Cursor