[jlb6740]

First of a series splitting #14696 into one PR per instruction class. Adds the
APX NDD (new data destination) forms of sub, and, or and xor for 64-bit
register-register ops, following the pattern #13916 established for add: an
RVM encoding promoted into EVEX map 4 with ND = 1, plus a lowering rule
guarded on use_apx. The separate destination means the register allocator no
longer needs a move to preserve a live input. has_apx is off by default, so
nothing changes unless it's enabled. More NDD patches to follow.

[jlb6740]

Note that this patch, and none of the patches to come based on #14969, are gated on the regalloc work bytecodealliance/regalloc2#267 and can go in before.

[fitzgen]

It would be interesting to check in instruction encoding whether the first operand and destination are (1) actually different registers or (2) in the new register set, and if neither is true then we should be able to use an old (more compact) encoding, correct? This would require a bit more machinery than currently exists, as I believe that we go immediately from MInst to assembler instruction encoding automatically, but seems like something that we should have a tracking issue for and would probably want to have before enabling APX by default on supported hardware.