Merge pull request #210 from brilliantlabsAR/raj/wip-cdc

Graphics CDC & auto clear

Author: siliconwitch

source/application/lua_libraries/display.c

@@ -293,14 +293,7 @@ static int lua_display_text(lua_State *L)
 
 static int lua_display_show(lua_State *L)
 {
-    // TODO remove blocking once we have a better solution
-
     spi_write(FPGA, 0x14, NULL, 0);
-    nrfx_systick_delay_ms(25);
-
-    spi_write(FPGA, 0x10, NULL, 0);
-    nrfx_systick_delay_ms(20);
-
     return 0;
 }
 

source/fpga/Makefile

@@ -24,7 +24,7 @@
 
 BUILD := ../../build
 TOOLCHAIN ?= YOSYS
-RADIANT_PATH ?= /opt/lscc/radiant/2023.1/bin/lin64
+RADIANT_PATH ?= /opt/lscc/radiant/2023.2/bin/lin64
 
 fpga_application.h: $(shell find . | egrep '.sv|.pdc')
 	@mkdir -p $(BUILD)

source/fpga/fpga_application.h

@@ -101,6 +101,9 @@ logic [3:0] display_ram_write_data;
 logic display_ram_write_enable_a;
 logic display_ram_write_enable_b;
 
+logic clear_flag;
+logic [18:0] clear_address_counter;
+
 display_buffer buffer_a (
     .clock(clock_in),
     .reset_n(reset_n_in),
@@ -121,7 +124,7 @@ display_buffer buffer_b (
     .write_enable(display_ram_write_enable_b)
 );
 
-// Buffer switching logic
+// Buffer switching & clearing logic
 enum logic {BUFFER_A, BUFFER_B} displayed_buffer;
 logic [1:0] switch_write_buffer_edge_monitor;
 logic buffer_switch_pending;
@@ -132,6 +135,8 @@ always_ff @(posedge clock_in) begin
         displayed_buffer <= BUFFER_A;
         switch_write_buffer_edge_monitor <= 'b00;
         buffer_switch_pending <= 0;
+        clear_flag <= 0;
+        clear_address_counter <= 0;
     end
 
     else begin
@@ -155,6 +160,17 @@ always_ff @(posedge clock_in) begin
             end
 
             buffer_switch_pending <= 0;
+
+            clear_flag <= 1;
+            clear_address_counter <= 0;
+        end
+
+        if (clear_flag == 1) begin
+            clear_address_counter <= clear_address_counter + 1;
+
+            if (clear_address_counter == 'd512000) begin
+                clear_flag <= 0;
+            end
         end
 
     end
@@ -171,12 +187,22 @@ always_ff @(posedge clock_in) begin
 
     else begin
         if (displayed_buffer == BUFFER_A) begin
-            display_ram_address_a <= pixel_read_address_in;
-            display_ram_address_b <= pixel_write_address_in;
+            if (clear_flag == 1) begin
+                display_ram_address_b <= clear_address_counter >> 1;
+            end else begin
+                display_ram_address_b <= pixel_write_address_in;
+            end
+
+            display_ram_address_a <= pixel_read_address_in; 
         end
 
         else begin
-            display_ram_address_a <= pixel_write_address_in;
+            if (clear_flag == 1) begin 
+                display_ram_address_a <= clear_address_counter >> 1;
+            end else begin
+               display_ram_address_a <= pixel_write_address_in; 
+            end
+
             display_ram_address_b <= pixel_read_address_in;
         end
     end
@@ -197,24 +223,31 @@ always_ff @(posedge clock_in) begin
 
     else begin
         pixel_read_data_out <= display_ram_read_data_b;
-
     end
 
 end
 
 // RAM writing logic
 always_ff @(posedge clock_in) begin
 
-    display_ram_write_data <= pixel_write_data_in;
-
-    // Select one of the four enables based on write address and selected buffer
-    display_ram_write_enable_a <= displayed_buffer == BUFFER_B && 
-                                  pixel_write_enable_in == 1
-                                ? 1 : 0;
+    if (clear_flag == 1) begin
+        display_ram_write_data <= 0;
+    end else begin
+        display_ram_write_data <= pixel_write_data_in;
+    end
 
-    display_ram_write_enable_b <= displayed_buffer == BUFFER_A && 
-                                  pixel_write_enable_in == 1
-                                ? 1 : 0;
+    if (pixel_write_enable_in == 1 || clear_flag == 1) begin
+        if (displayed_buffer == BUFFER_A) begin
+            display_ram_write_enable_a <= 0;
+            display_ram_write_enable_b <= 1;
+        end else begin
+            display_ram_write_enable_a <= 1;
+            display_ram_write_enable_b <= 0;
+        end
+    end else begin
+        display_ram_write_enable_a <= 0;
+        display_ram_write_enable_b <= 0;
+    end
 
 end