Editor S.T. (LinkedIn)
WeChat / 微信公众号 · StarryHeavensAbove — AI chip articles
A living directory of AI accelerators (ICs & IPs) — each entry has a short field intro (plus lineage where relevant) and 1–2 latest updates. Prefer official / primary sources; performance claims are often vendor-reported.
Explore: AI Accelerator Software Ecosystem · AI Accelerator Benchmarks · Compatibility Explorer
One-line latest status per company — updated periodically. Last refreshed: November 2026. Detailed software and benchmark maps are maintained in dedicated pages.
- NVIDIA — Vera Rubin platform in full production (GTC 2026); NVL72 partner shipments targeted H2 2026.
- Intel / Habana — Gaudi 3 generally available on IBM Cloud and Dell AI Factory for enterprise GenAI inference/fine-tune.
- AMD — Helios / MI455X rack-scale on track for H2 2026; Meta 6GW Instinct deal incl. custom MI450-class.
- Qualcomm — Dragonfly data-center AI: AI200/AI250 (2026–27) + AI300/HBC; Meta multi-gen deal for Dragonfly C1000 CPU.
- Samsung — Exynos 2600 (first 2nm GAA mobile SoC) ships in Galaxy S26 with large on-device GenAI NPU gains.
- MediaTek — Dimensity 9500 (Sep 2025) NPU 990 + Super Efficient CIM NPU for agentic on-device GenAI.
- Marvell — Custom AI XPU partner for AWS Trainium / Microsoft Maia; 18+ custom projects and rising AI silicon revenue.
- Broadcom — OpenAI Jalapeño Intelligence Processor unveiled; continues Google TPU + Meta MTIA XPU franchise.
- Google — Ironwood (TPU7x) generally available Mar 2026; Trillium (v6e) remains a volume Cloud TPU SKU.
- AWS — Trainium3 / Trn3 UltraServers GA (Dec 2025); Trainium4 previewed with NVLink Fusion path.
- Microsoft — Maia 200 inference accelerator (Jan 2026) deploying in Azure for Copilot / Foundry token economics.
- OpenAI — First custom inference ASIC “Jalapeño” with Broadcom; initial deployments targeted end of 2026.
- Anthropic — Expanded Google TPU + Broadcom capacity (~3.5 GW from 2027) atop AWS Trainium and NVIDIA GPUs.
- Apple — M5 / M5 Pro / M5 Max add GPU Neural Accelerators and a faster Neural Engine for Apple Intelligence.
- Alibaba — Zhenwu M890 (144GB HBM3) in mass production; 560k+ Zhenwu shipments; roadmap to V900/J900.
- Baidu — Kunlunxin P800 10k-card clusters; key ERNIE 5.1 training on domestic stack; Tianchi 256-card supernode (2026).
- Tencent — Zixiao / partner accelerators continue scaling LLM and recommendation serving on Tencent Cloud (2025–2026).
- Meta — MTIA “Iris” (v3) enters production Sep 2026 with Broadcom/TSMC; six-month chip cadence through 2027.
- Tesla — AI5 taped out (Apr 2026); AI6 / Dojo3 in progress; vehicles near-term stay on AI4.
- Arm — Ethos-U85 + Corstone-320 IoT reference for edge transformer / GenAI; Armv9 SME path in mobile SoCs.
- Synopsys — ARC NPX NPU IP scaled for auto/consumer GenAI SoCs with ongoing 2025–2026 toolchain releases.
- Imagination — PowerVR NNA + Continuum for edge/auto transformer networks; 2025–2026 licensee SoC ramps.
- CEVA — NeuPro-class NPU IP for embedded/auto/IoT transformers; 2025–2026 DNN compiler updates.
- Cadence — Tensilica AI Platform / NeuroWeave updates for on-device and automotive transformer SoCs (2025–2026).
- VeriSilicon — VIP/Acuity NPU IP and turnkey services for China/global edge GenAI SoCs (2025–2026).
- Cerebras — Nasdaq IPO (CBRS, May 2026); multi-year OpenAI inference capacity deal (>$20B messaging).
- Graphcore — SoftBank injects ~$457M (2026); Izanagi next-gen IPU+CPU path aimed at Stargate-scale 2026 deployments.
- Tenstorrent — Galaxy Blackhole GA (Apr 2026): 32× Blackhole servers shipping for LLM inference and video gen.
- Etched — ~$5B valuation / ~$1B booked orders for transformer-specialized Sohu inference ASICs.
- Groq — LPU technology licensed into NVIDIA’s Vera Rubin AI-factory stack (GTC 2026).
- SambaNova — SN50 RDU for agentic AI; $350M+ Series E; SoftBank early deploy; Intel collab; H2 2026 ship.
- Mythic — $125M Series D + Videantis acquisition for hybrid analog/digital energy-efficient inference.
- Hailo — Hailo-10H generally available for edge LLMs/VLMs (~40 TOPS INT4 class, ~2.5W).
- FuriosaAI — RNGD in mass production; Broadcom partnership for next-gen multi-die inference platform.
- Kinara — NXP acquiring Kinara (ex–Deep Vision) for industrial/automotive edge NPU portfolio.
- SiMa.ai — Modalix MLSoC in production for Physical AI (robots/industrial) under ~10W with LLiMa LLMs.
- d-Matrix — Corsair inference platform in full production (Jun 2026); $275M Series C / ~$2B valuation.
- Blaize — Nasdaq-listed (BZAI); GSP architecture for industrial/smart-city edge vision and GenAI.
- SynSense — Speck/Xylo neuromorphic + event-vision stack; 2025–2026 funding/collabs for ultra-low-power edge AI.
- Sagence AI — Analog CIM accelerators for efficient LLM/vision inference; active 2025–2026 AI-infra engagements post-rebrand.
- Huawei Ascend — Atlas 950 SuperPoD / Ascend 950DT (up to 8,192 NPUs) debuts globally at MWC 2026; WAIC hardware showcase.
- Cambricon — Siyuan 690 in mass production/delivery; targets ~500k AI chips in 2026; Q1 profit surge on cloud demand.
- Biren — Hong Kong IPO (6082.HK, Jan 2026); BR100-class GPGPU/AI accelerators.
- Moore Threads — STAR Market IPO Dec 2025; MTT S4000/S5000 AI GPUs with MUSA software stack.
- MetaX — STAR-listed (688802.SH); C500 in mass production, C600 domestic-process follow-on, MXMACA stack.
- Hygon — DCU GPGPUs + DTK stack; Day-0 DeepSeek-V4 adaptation alongside Ascend and Cambricon.
- Iluvatar CoreX — HK-listed; multi-gen GPU roadmap (Tianshu→Tianquan) aiming at Hopper–Rubin class gap; BI-V150 deployed.
- Enflame — CloudBlazer / iGCU GPUs in China ICC deployments; TopsRider LLM stack updates through 2025–2026.
- Horizon Robotics — Journey 6 / BPU Nash mass-designed into China L2+ vehicles; stronger Transformer / E2E driving support.
- Black Sesame — Huashan A1000 in mass-production vehicles; A2000 messaging for higher-perf / cross-domain AD (2025–2026).
NVIDIA turned GPUs into the default AI training/inference substrate via CUDA (2007) and successive datacenter architectures. From Pascal/Volta Tensor Cores through Ampere and Hopper, the stack evolved into rack-scale Grace+Blackwell systems; Rubin extends that AI-factory model into 2026.
CUDA foundation (pre–Tensor Core)
- Tesla arch (2006) + CUDA (2007) — unified shaders / GPGPU; GPU becomes a general accelerator.
- Fermi (2010) — caches, ECC, stronger HPC path.
- Kepler (2012) — Hyper-Q / dynamic parallelism; datacenter Tesla K-series.
- Maxwell (2014) — major perf/W redesign.
- Pascal (2016) — P100 — HBM2 + NVLink 1.0; first widely adopted datacenter GPU for deep learning at scale.
Tensor Core era
- Volta (2017) — V100 — first Tensor Cores (FP16 mixed precision); DGX / early large-model workhorse.
- Turing (2018) — T4 — inference-efficient datacenter SKUs; consumer RTX adds RT + Tensor Cores.
- Ampere (2020) — A100 — TF32 / BF16, structured sparsity, MIG; A100 40/80GB HBM2e.
- Ada Lovelace (2022) — L40 / L4 — inference / visual datacenter SKUs alongside Hopper.
- Hopper (2022) — H100 / H200 — Transformer Engine, FP8, NVLink 4; H200 expands HBM3e for LLM train/serve.
Platform / rack-scale era (2024–2026)
- Blackwell (2024) — B200 / GB200 NVL72 — multi-die GPU, FP4/FP6 datapaths, NVLink 5; Grace+Blackwell superchips and NVL72 racks.
- Rubin (CES/GTC 2026) — Vera CPU + Rubin GPU + NVLink 6 Switch + ConnectX-9 / BlueField-4 / Spectrum-6 for agentic / MoE; partner availability targeted H2 2026. NVIDIA also described integrating Groq-class LPU technology into the AI-factory stack.
Latest
- Vera Rubin opens agentic AI frontier — GTC Mar 2026 — seven chips in full production (Vera CPU, Rubin GPU, NVLink 6, ConnectX-9, BlueField-4, Spectrum-6, Groq LPU); NVL72 on track for H2 2026 partner systems.
- Vera Rubin POD / rack-scale systems — Mar 2026 — POD-scale co-design across five rack systems; CEO later reiterated “giant amounts” of Vera Rubin production incoming for H2 2026.
Hopper in-depth · Hopper · Blackwell
Intel’s AI accelerator path consolidated around Habana Labs after the 2019 acquisition. Gaudi (training) and Goya (inference) established Ethernet-centric scale-out as an alternative to proprietary GPU fabrics; Gaudi 2 broadened LLM training, and Gaudi 3 (2024) targets enterprise generative AI with OEM and cloud availability. Intel also folds AI into Xeon AMX and Arc/Flex GPUs, but Gaudi remains the dedicated datacenter accelerator brand.
Latest
- Gaudi 3 on IBM Cloud — Intel Vision 2025 — IBM Cloud is the first CSP with Gaudi 3 in production (Frankfurt, Washington D.C., Dallas) for enterprise GenAI price/performance.
- Dell AI Factory with Gaudi 3 — 2025 — Dell AI platform / AI Factory ships validated Gaudi 3 systems for scalable enterprise GenAI with open Ethernet networking.
AMD’s datacenter AI story runs through the Instinct line on CDNA architecture (distinct from RDNA gaming GPUs), with ROCm as the software stack. MI100/MI200 established HBM-heavy training SKUs; MI300A/X (CDNA 3, 2023) brought chiplet APU/GPU designs into large LLM clusters. MI350 (CDNA 4, 2025) pushes HBM3E capacity and low-precision datatypes; MI400 / Helios rack systems headline the 2026 roadmap alongside deep hyperscaler partnerships.
- MI100 / MI200 (CDNA 1–2) — early Instinct training accelerators; MI250X widely used in HPC+AI.
- MI300A / MI300X (2023) — CDNA 3 chiplets; MI300X became a primary non-NVIDIA LLM training/inference GPU.
- MI350X / MI355X (2025) — CDNA 4, up to 288GB HBM3E, MXFP6/MXFP4 paths.
- MI400 / Helios (roadmap 2026) — rack-scale systems and custom SKUs for hyperscalers.
Latest
- AMD–Meta 6GW Instinct partnership — Feb 2026 — up to 6GW multi-generation Instinct GPUs; custom MI450-class on Helios with ROCm; first-GW shipments targeted H2 2026.
- Helios / MI400 series on track — 2026 — AMD says Helios racks and MI400/MI455X UALink systems remain on track for H2 2026 engineering/low-volume production alongside MI350 volume deployments.
Qualcomm’s AI silicon now spans mobile Hexagon NPUs in Snapdragon SoCs and a full data-center Dragonfly portfolio for agentic inference. Hexagon evolved from DSP blocks into fused scalar/vector/tensor NPUs for on-device GenAI; Cloud AI 100 was an earlier inference SKU. In Oct 2025 Qualcomm launched rack-scale Dragonfly AI200/AI250 inference accelerators, then at Investor Day Jun 2026 added AI300 with High Bandwidth Compute (HBC), the Dragonfly C1000 server CPU (Meta multi-generation agreement), and a multi-year data-center revenue push.
Latest
- Dragonfly AI300 / data-center roadmap — Jun 24, 2026 Investor Day — Dragonfly AI300 (3rd-gen rack inference with HBC Gen 2; sampling ~2028) joins AI200/AI250; Dragonfly C1000 CPU (250+ Oryon cores) with multi-generation Meta server deal; HBC near-memory compute for token efficiency.
- Dragonfly AI200 / AI250 launch — Oct 2025 — Hexagon-based rack-scale inference accelerators: AI200 (~768GB LPDDR/card, commercial ~2026) and AI250 (HBC Gen 1 near-memory, ~2027); Humain among early large deploy partners.
Samsung integrates NPUs into Exynos mobile SoCs and builds HBM that underpins datacenter AI GPUs. Exynos NPUs scaled with each flagship for vision and on-device GenAI; Exynos 2500 (3nm GAA) was followed by Exynos 2600 — Samsung’s first 2nm GAA mobile SoC — powering Galaxy S26 with substantially higher generative-AI NPU performance and AI graphics features (ENSS).
Latest
- Exynos 2600 — First 2nm GAA mobile SoC; Samsung cites ~113% generative-AI NPU gains vs. prior gen for larger on-device models; ships in Galaxy S26 / S26+.
- ENSS AI graphics on Exynos 2600 — Apr 2026 — Exynos Neural Super Sampling (ENSS) commercialized for AI upscaling/frame generation to cut GPU load on flagship gaming/graphics.
MediaTek’s Dimensity flagship line pairs Arm CPUs with successive in-house NPUs for Android on-device AI. The NPU roadmap (through 8th-gen NPU 890 on Dimensity 9400) emphasizes generative and agentic workloads—LoRA adaptation, diffusion video, and MoE LLMs—alongside the Dimensity Agentic AI Engine software path.
Latest
- Dimensity 9500 — NPU 990 — Sep 2025 — 9th-gen NPU 990 with Generative AI Engine 2.0 (vendor: ~2× compute, 4K image gen, 128K-token LLM path) plus Super Efficient CIM NPU for always-on AI.
Marvell supplies DPUs (OCTEON / ARMADA) and, increasingly, co-designed custom AI accelerators for cloud providers. Alongside Broadcom’s XPU franchise, Marvell is widely reported as a design partner on AWS Trainium/Inferentia-class and Microsoft Maia-class silicon—making it a key “picks and shovels” vendor in the custom-ASIC wave.
Latest
- Expanding custom silicon opportunity — Jul 2025 — Custom AI Investor Event: ~18 active custom projects (hyperscaler XPUs + attach) with TAM for custom XPUs growing into the tens of billions by 2028.
- Hyperscaler AI ASIC programs — 2025–2026 — widely reported design partner on AWS Trainium-class and Microsoft Maia-class accelerators, plus AI optics/DPU attach silicon.
Broadcom co-designs customer-specific AI accelerators (XPUs) and pairs them with Tomahawk/Jericho Ethernet switching. The model began with Google TPU generations and now spans Meta MTIA, OpenAI custom silicon, and other frontier/cloud programs—positioning Broadcom as the primary ASIC implementation partner opposite merchant GPUs.
Latest
- OpenAI Jalapeño with Broadcom — Jun 2026 — OpenAI’s first custom LLM inference ASIC co-developed with Broadcom (Tomahawk networking); initial deployments targeted end of 2026 within multi-GW platform.
- Meta MTIA partnership extended — Apr 2026 — XPU platform continues as co-design backbone for multi-generation MTIA and Ethernet AI fabric.
Google invented the modern custom-AI-ASIC pattern with TPU v1 (2015) for production inference, then opened Cloud TPU for external training. Each generation scaled systolic MXUs, HBM, and pod interconnect; v4/v5 pods trained many Google foundation models, while Trillium (v6e) and Ironwood (v7) address GenAI train/serve economics. Edge TPU (Coral) and Pixel Tensor are related but separate product lines.
Early generations
- TPU v1 (2015) — inference-only systolic MXU (INT8) in Google production services.
- TPU v2 (2017) — training + inference, bfloat16, HBM, first multi-chip pods.
- TPU v3 (2018) — higher compute, liquid cooling at pod scale.
- TPU v4 (2021) — denser pods, 3D torus + optical circuit switches.
Split SKUs & GenAI scale-up
- TPU v5e (2023) — cost-efficient training/inference at volume.
- TPU v5p (2023) — high-end large-pod training.
- Trillium / TPU v6e (2024) — larger MXUs; Google cites ~4.7× peak compute/chip vs. v5e.
- Ironwood / TPU v7 (2025) — inference-leaning generation with FP8-class paths and very large pods.
Related Google silicon
- Edge TPU — Coral edge inference ASIC.
- Google Tensor (Pixel) — mobile SoC ML blocks (separate from Cloud TPU).
Latest
- Ironwood (TPU7x) GA — Mar 31, 2026 — TPU7x (Ironwood family) generally available for large-scale training and inference (LLMs, MoEs, diffusion); up to 9,216-chip pods.
- Ironwood for the age of inference — 2025–2026 — 7th-gen TPU purpose-built for high-volume low-latency inference/serving; Google cites large per-chip gains vs. prior gen.
10 years of TPU · v6e docs · Cloud TPU · Edge TPU
AWS builds first-party AI silicon for EC2: Inferentia for inference and Trainium for training, compiled via the Neuron SDK. Inferentia1/2 lowered LLM serving cost on Inf1/Inf2; Trainium1 and Trainium2 (Trn1/Trn2) plus UltraServers with NeuronLink scale-up target foundation-model training and large inference inside AWS regions—often co-designed with partners such as Marvell/Annapurna.
Latest
- EC2 Trn3 UltraServers (Trainium3) — Dec 2025 re:Invent — Trainium3 (first 3nm AWS AI chip) UltraServers GA; AWS cites up to ~4.4× compute and ~4× energy efficiency vs. Trn2 UltraServers.
- Trainium3 UltraServers details — Up to 144 Trainium3 chips / ~362 FP8 PFLOPs per UltraServer; Anthropic and Bedrock among early Trainium users; Trainium4 on the roadmap.
Microsoft entered custom AI silicon with Azure Maia (accelerator) and Cobalt (Arm CPU) to optimize Azure OpenAI / Copilot economics. Maia 100 (5nm, advanced packaging) is co-designed for Azure AI cloud workloads with a PyTorch/ONNX Runtime software path; subsequent Maia generations are expected to deepen rack-level integration with Azure networking and cooling.
Latest
- Maia 200 inference accelerator — Jan 2026 — TSMC 3nm inference ASIC with 216GB HBM3e; Microsoft cites ~30% better perf/$ vs. prior fleet hardware and FP4/FP8 leadership claims vs. other custom silicon.
- Maia 200 Azure rollout — Deploying in US Central (then US West 3) for Superintelligence / Foundry / Copilot workloads; Maia SDK preview with PyTorch and Triton.
Long dependent on NVIDIA GPUs (and Azure capacity), OpenAI moved into custom inference silicon to cut serving cost and diversify supply. Jalapeño—co-developed with Broadcom—is the first “Intelligence Processor,” optimized for LLM inference rather than general training, as the opening move in a multi-generation, multi-gigawatt Broadcom collaboration.
Latest
- Jalapeño LLM inference chip — Jun 2026 — first custom inference-optimized ASIC with Broadcom; initial deployments targeted by end of 2026 within a multi-generation platform.
Anthropic does not tape out a merchant chip brand; it co-designs capacity across AWS Trainium (Project Rainier), Google TPUs (Broadcom-implemented), and NVIDIA GPUs. The strategy is deliberate multi-sourcing for Claude training and serving at gigawatt scale, with long-term TPU commitments expanding through 2027+.
Latest
- Google & Broadcom compute partnership — Apr 2026 — expanded multi-GW next-gen TPU capacity (filings cite ~3.5 GW) from 2027, on top of prior >1 GW TPU plus Trainium and NVIDIA.
Apple’s on-device AI runs on the Neural Engine and, increasingly, GPU Neural Accelerators inside Apple silicon—not discrete datacenter GPUs. From A11’s first Neural Engine through M1–M4, Apple scaled unified-memory ML performance for privacy-preserving inference; M5 (2025) and M5 Pro/Max (2026) explicitly target Apple Intelligence and local LLM/creative AI workflows.
Latest
- Apple M5 — Oct 2025 — Neural Accelerators in each GPU core and a faster 16-core Neural Engine for on-device Apple Intelligence.
- M5 Pro and M5 Max — Mar 2026 — Fusion Architecture scales GPU AI compute and unified memory (up to 128GB / ~614GB/s on M5 Max) for local LLM and pro creative AI.
Alibaba’s T-Head unit designs cloud AI accelerators under the Zhenwu / PPU family for Alibaba Cloud and external customers as a domestic GPU-class alternative. After Zhenwu 810E-class SKUs, Zhenwu M890 (2026) raises HBM capacity and chip-to-chip bandwidth for agentic train/infer, paired with Panjiu AL128 servers, ICN Switch networking, and the SAIL software stack.
Latest
- Zhenwu M890 AI chip — May 2026 Cloud Summit — M890 triples prior-gen performance claims with 144GB HBM3 and 800GB/s chip-to-chip bandwidth; FP32→FP4; powers Panjiu AL128 with ICN Switch 1.0.
- T-Head scale shipments — 2026 — T-Head cites 560,000+ Zhenwu AI chips shipped and 400+ external customers; further V900 (2027) / J900 (2028) roadmap messaging.
Baidu’s Kunlunxin (昆仑芯) GPUs underpin ERNIE and Baidu Cloud AI services. From earlier Kunlun generations through P800-class training/inference cards, Baidu has iterated a full stack (hardware + software) as a China-domestic alternative for large-model workloads.
Latest
- Kunlunxin trains key ERNIE 5.1 version — Baidu Create 2026 — P800 completed large-scale validation with multiple 10k-card clusters since 2025; fully domestic Kunlunxin cluster trained a key ERNIE 5.1 version (97% effective training rate claimed).
- Tianchi 256-card supernode — May 2026 — Tianchi 256-card Kunlunxin supernode lit up, June launch messaging; +25% throughput / +50% inference efficiency claims vs. prior gen, HPN5.0 networking.
Tencent deploys proprietary Zixiao-class and partner AI accelerators across Tencent Cloud for recommendation, multimodal, and LLM train/infer inside its China footprint—part of a broader mix that also includes merchant GPUs where available.
Latest
- Tencent Cloud AI accelerators — 2025–2026 — proprietary Zixiao-class and partner AI accelerators deployed for recommendation, multimodal, and LLM train/infer inside Tencent Cloud.
Meta’s MTIA (Meta Training and Inference Accelerator) is an in-house family for ranking, recommendation, and increasingly generative workloads at hyperscale. Built with Broadcom as implementation partner, MTIA has moved to a rapid multi-generation chiplet cadence (MTIA 300–500 class messaging) aimed at Meta’s production AI fleet rather than merchant sale.
Latest
- MTIA Iris production September 2026 — Jul 2026 reporting — next-gen MTIA chip (Iris / v3) cleared testing and targets September production with Broadcom design + TSMC 3nm; part of ~6-month cadence through 2027.
- Four MTIA chips in two years — Multi-generation MTIA roadmap (300–500 class) with modular chiplets; continues alongside AMD Instinct and NVIDIA GPU capacity.
Tesla designs FSD/AI inference SoCs for vehicles (HW3 → HW4/AI4 → AI5) and pursued Dojo training tiles for internal vision-model training. The vertical stack ties cars, Optimus, and data-center inference together; AI5 is the next major SoC step after AI4, with Dojo3 still on the longer training roadmap.
Latest
- Tesla AI5 taped out — Apr 2026 — AI5 inference/training SoC taped out; AI6/Dojo3 mentioned as in progress; broad vehicle deployment still gated (reports: mid–late 2027+).
Arm licenses Ethos NPU IP alongside Cortex CPUs for edge and IoT SoCs. The Ethos-U micro-NPU line (U55 → U65 → U85) scales MAC arrays and adds transformer operators while keeping the Vela/Ethos toolchain path; larger Ethos-N products address higher-TOPS vision/GenAI in Cortex-A systems.
Latest
- Ethos-U85 micro-NPU — Third-gen Ethos-U (to ~4 TOPS @ 1 GHz) with native transformer ops for edge/IoT GenAI; Corstone-320 reference and Vela toolchain.
- Arm C1 / SME2 in flagship SoCs — 2025 — Arm Lumex CSS (C1 cores + SME2) ships in MediaTek Dimensity 9500-class SoCs, accelerating on-CPU ML alongside NPUs.
Synopsys DesignWare ARC NPX provides licensable neural processor IP for SoC integrators across automotive, consumer, and infrastructure. The family emphasizes scalable TOPS, functional-safety options, and toolchain continuity for DNN/transformer graphs.
Latest
- ARC NPX NPU IP — 2025–2026 — DesignWare ARC NPX neural processor IP for automotive/consumer/infrastructure SoCs; multi-TOPS configs and transformer-ready toolchain updates.
Imagination’s PowerVR Neural Network Accelerators (NNA) and GPU+NNA combinations target edge and automotive SoCs. IMG Continuum software maps CNN and transformer-class networks onto the NNA datapaths for licensees.
Latest
- Imagination AI / NNA IP — 2025–2026 — PowerVR Neural Network Accelerators and GPU+NNA combinations for edge and automotive SoCs with Continuum software for transformer-class nets.
CEVA licenses low-power AI processor IP and DSP/NPU hybrids for real-time embedded, automotive, and IoT inference. NeuPro-class offerings and the CEVA DNN compiler add transformer-capable paths for on-device GenAI and vision.
Latest
- CEVA edge AI / NeuPro IP — 2025–2026 — low-power NeuPro-class AI processor IP and DNN graph compiler for real-time embedded, automotive, and IoT inference including transformers.
Cadence Tensilica offers configurable NPU and AI DSP IP for on-device and automotive SoCs. The NeuroWeave toolchain maps modern DNN and transformer graphs onto Tensilica datapaths used widely in vision, audio, and edge GenAI chips.
Latest
- Tensilica AI Platform — 2025–2026 — Tensilica NPU/AI DSP IP with NeuroWeave toolchain updates for modern DNN and transformer workloads in edge/auto SoCs.
VeriSilicon provides VIP/Acuity NPU IP plus turnkey ASIC design services, especially strong in China edge and vision SoCs. The IP covers CNN through on-device GenAI use cases for consumer, automotive, and IoT customers.
Latest
- VIP / NPU IP & design services — 2025–2026 — Acuity/VIP NPU IP plus turnkey ASIC design services widely used in China and global edge SoCs for vision and on-device GenAI.
Cerebras builds wafer-scale AI processors (WSE) that place an enormous on-wafer SRAM/compute fabric into CS systems, avoiding many multi-GPU communication bottlenecks. WSE-1/2 established the approach; WSE-3 (2024, 5nm) powers CS-3 for foundation-model training and high-throughput inference with cloud and on-prem deployments.
Latest
- Cerebras IPO (CBRS) — May 2026 — blockbuster Nasdaq debut after filing; WSE-3 / CS-3 wafer-scale systems power Training and Inference Cloud services.
- OpenAI multi-year capacity deal — 2025–2026 — OpenAI commits to large inference capacity (filings cite 750MW committed, option to 2GW) plus $1B infrastructure loan / warrants.
Graphcore pioneered Intelligence Processing Units (IPU) with fine-grained MIMD parallelism and large on-chip memory (Colossus Mk1/Mk2, Bow). After competing in the pre-LLM and early-LLM era, SoftBank acquired Graphcore (2024) as a wholly owned subsidiary to fund next-generation AI compute while keeping the Graphcore brand.
Latest
- SoftBank $457M funding into Graphcore — May 2026 — SoftBank funnels ~$457M into Graphcore (wholly owned since Jul 2024) to fund next-gen AI silicon and SoftBank AI infra plans.
- Izanagi / SoftBank AI stack — 2025–2026 — next-gen accelerator work (Izanagi messaging) pairs Graphcore IPU heritage with SoftBank/Ampere Arm CPU stack for hyperscale deployment targets.
Tenstorrent (Jim Keller–led) builds Tensix-based AI processors as scalable chiplet meshes with an open software stack (TT-Metalium). Wormhole-generation cards are shipping into developer and rack deployments; Blackhole is the next architecture step toward higher-density train/infer systems.
Latest
- Galaxy Blackhole general availability — Apr 28, 2026 — 6U air-cooled Galaxy with 32 Blackhole chips shipping (vendor: 23 PFLOPS Block FP8, Ethernet scale-out); from ~$110k per server.
- TT-Deploy production shipping — May 2026 — TT-Deploy: volume shipping, multi-Galaxy superclusters, open TT-Metalium stack, and third-party validated serving benchmarks.
Etched builds ASICs purpose-built for Transformer inference (Sohu) rather than general-purpose GPU programmability—betting that specialization wins tokens/sec and energy efficiency for LLM serving. TSMC-manufactured silicon and “frontier inference cluster” messaging mark a fast rise from 2024 Series A through 2026 scale-up.
Latest
- Etched hits $5B valuation — Jun 2026 — ~$800M raised to date (incl. $500M at $5B valuation) and ~$1B in booked system orders for transformer-specialized ASICs.
Groq’s Language Processing Unit (LPU) uses a deterministic, compiler-scheduled architecture for ultra-low-latency LLM token generation. After building a cloud inference service on LPU racks, Groq’s technology was licensed by NVIDIA (late 2025), with key talent joining NVIDIA; GTC 2026 described LPU-class engines inside the Vera Rubin AI factory for efficient decode alongside Rubin GPUs.
Latest
- NVIDIA Vera Rubin includes Groq LPU — Late 2025 NVIDIA licensed Groq LPU tech; GTC 2026 — LPU-class engines integrated into Vera Rubin for low-latency / high-efficiency token generation.
SambaNova’s Reconfigurable Dataflow Unit (RDU) maps full model graphs onto a dataflow fabric for enterprise and agentic inference. SN40L established the GenAI-era platform; SN50 (5th gen) scales compute and network bandwidth for large agentic deployments with SambaNova’s full-stack software.
Latest
- SN50 RDU, Intel collab, $350M+ Series E — Feb 2026 — SN50 targets agentic inference (vendor: ~5× compute / ~4× network vs. SN40L); SoftBank early deploy; H2 2026 shipping; Intel heterogeneous-inference collaboration.
Mythic builds Analog Processing Units (APUs) that use flash-based compute-in-memory for energy-efficient inference at the edge and in data centers. After years of analog AI development, 2025–2026 funding and the Videantis acquisition add digital processor IP for a hybrid analog/digital platform aimed at robotics, automotive, and defense.
Latest
- $125M Series D — Dec 2025 — oversubscribed DCVC-led round (Honda, Lockheed Martin among strategics) to scale APUs and chiplet next-gen products.
- Acquires Videantis — May 2026 — Videantis digital processor IP + software joins Mythic analog CIM for a hybrid efficiency-focused platform.
Hailo designs high-efficiency edge AI accelerators for vision and, with Hailo-10, on-device generative AI. Hailo-8 established the structure-sparsity / efficient-NPU brand in smart cameras and industrial vision; Hailo-10H adds LLM/VLM-class GenAI at low watts with automotive qualification paths.
Latest
- Hailo-10H GA for edge GenAI — Jul 2025 — second-gen Hailo-10H for on-device LLM/VLM/GenAI (~40 TOPS INT4, ~2.5W typical); AEC-Q100 Grade 2 with 2026 SOP targeting.
Korea-based FuriosaAI builds Tensor Contraction Processor (TCP) accelerators for datacenter inference. After earlier Warboy edge/vision chips, RNGD (TSMC 5nm) targets LLM and agentic serving in air-cooled multi-card servers, with a Broadcom collaboration to scale into multi-die Ethernet/PCIe platforms.
Latest
- RNGD mass production — Jan 2026 — RNGD (~180W PCIe) volume shipment for LLM/agentic inference; NXT RNGD servers pack multiple cards into ~3kW-class air-cooled systems.
- Broadcom inference partnership — May 2026 — evolve TCP into a scale-up multi-die inference platform with Broadcom Ethernet/PCIe switching.
Kinara (formerly Deep Vision) builds Ara/Prisma-class edge NPUs for vision and on-device GenAI inference. The company rebranded and scaled edge AI SKUs before NXP announced an acquisition (2025) to fold Kinara into NXP’s industrial and automotive edge AI portfolio.
Latest
- NXP to acquire Kinara — Feb 2025 — NXP acquisition of Kinara for edge AI NPUs used in vision and on-device GenAI; expands NXP industrial/automotive AI.
SiMa.ai builds MLSoC platforms for edge / Physical AI—robots, industrial, automotive, and vision—combining CPU, ML accelerator, and software (Palette / LLiMa) for CNN through Transformer/LLM workloads at low power. Modalix is the second-generation production platform after the first MLSoC.
Latest
- Modalix platform in production — Aug 2025 — Modalix ships for Physical AI under ~10W with SoM/devkits and LLiMa for on-device LLM deployment.
d-Matrix builds digital compute-in-memory accelerators (Corsair) for low-latency, high-efficiency datacenter LLM inference—contrasting analog CIM approaches with a digital datapath while still attacking the memory-wall bottleneck that dominates decode.
Latest
- Corsair enters full production — Jun 2026 — Corsair digital in-memory inference platform in volume production (TSMC N6); shipping to priority hyperscalers, neoclouds, and frontier labs.
- Series C / $2B valuation — Nov 2025 — $275M Series C (incl. Microsoft M12) at ~$2B valuation to scale Corsair rack-scale inference.
Blaize’s Graph Streaming Processor (GSP) targets graph-native edge AI for vision and GenAI in industrial and smart-city deployments. After years as a private edge-AI vendor, Blaize listed via SPAC (Nasdaq: BZAI) in 2025 to scale product and go-to-market.
Latest
- Blaize AI edge platforms — 2025 — listed via SPAC; GSP architecture for edge AI vision / GenAI in industrial and smart-city deployments.
SynSense (formerly aiCTX) builds neuromorphic and event-based sensing+compute chips (Speck, Xylo) for ultra-low-power always-on perception. Collaborations such as with iniVation extend event-camera + neuromorphic pipelines for edge AI.
Latest
- SynSense neuromorphic products — 2025–2026 — Speck/Xylo-class neuromorphic chips and event-based vision+compute offerings (incl. prior iniVation collaboration) for always-on edge sensing.
Sagence AI (rebranded from Analog Inference in Nov 2024) develops analog compute-in-memory accelerators aimed at energy-efficient LLM and vision inference for datacenter and edge deployments—part of the broader analog-AI cohort seeking orders-of-magnitude efficiency vs. digital GPUs on inference.
Latest
- Sagence AI analog CIM — 2025–2026 — continues analog compute-in-memory accelerators (ex–Analog Inference) aimed at energy-efficient datacenter/edge LLM and vision inference.
Domestic training/inference accelerators have become central under export-control and procurement policies. Coverage below highlights widely reported product lines; treat performance claims as vendor-/press-reported unless independently benchmarked.
Huawei’s Ascend line (HiSilicon) is China’s most widely deployed domestic training/inference accelerator family. Ascend 910 established the high-end; 910B/910C scaled under export controls into Atlas servers and SuperPoD / CloudMatrix supernodes. Ascend 950-class (950DT training / 950PR inference messaging) and Atlas 950 SuperPoD push UnifiedBus optical scale-up to thousands of NPUs as a single logical node, with Cann/MindSpore as the software stack.
Latest
- Atlas 950 SuperPoD at MWC 2026 — Mar 2026 — global debut of Atlas 950 SuperPoD on UnifiedBus; scales from 64 NPUs/cabinet toward up to 8,192 Ascend 950-class NPUs for large-model train/infer.
- Atlas 950 SuperPoD at WAIC 2026 — Jul 2026 — first public hardware demonstration planned at WAIC Shanghai; single-cabinet 64-card base with global unified memory addressing for trillion-parameter models.
Cambricon is China’s leading pure-play AI-chip vendor, spanning edge IP/SoCs and cloud MLU / Siyuan accelerators. After an early edge-IP era, the company refocused on cloud training/inference cards for Chinese internet and intelligent-computing customers, with aggressive 2026 volume plans.
Latest
- Siyuan 690 mass production — 2026 — next-gen Siyuan/MLU 690 cloud accelerators in mass production/delivery (reports: dual-die, ~196GB HBM3, >700 TFLOPS FP16-class); Q1 profit surged on domestic cloud demand.
- 500,000 AI chips target for 2026 — Aggressive 2026 volume plans for Siyuan 590/690-class accelerators serving Chinese internet/cloud customers as a leading pure-play domestic AI-chip vendor.
Biren develops general-purpose GPU-class accelerators for data-center AI training and inference. The BR100 family established its high-performance GPGPU direction; subsequent BR-series products and system offerings should be tracked by exact SKU and deployment status rather than treating the family as one device. The company listed in Hong Kong in January 2026 (6082.HK).
Hardware and system direction
- BR100 family — multi-die GPGPU architecture and high-bandwidth memory, an important reference point in Biren's early data-center product roadmap.
- BR-series product updates — track each announced board / OAM / PCIe SKU separately, including memory configuration, cooling, power envelope, supported server platforms, and whether it is sampling, shipping, or deployed.
- Cluster and interconnect — evaluate multi-accelerator scaling, collective communication, and system-level integration rather than comparing peak compute alone.
Software ecosystem: BIRENSUPA
- BIRENSUPA — Biren's software development platform; track compiler, runtime, operator libraries, framework integrations, profiling and debugging tools as separately versioned components.
- Compatibility evidence — record exact accelerator SKU, SDK release, framework version, model coverage, and tested serving engine. Do not infer upstream vLLM / SGLang support from a general platform announcement.
Latest
- Hong Kong listing — Jan 2026 — listed as 6082.HK; financing and production scale-up are important company milestones.
- Biren official site — use the product and platform pages as the primary source for current BR-series SKUs and BIRENSUPA capabilities.
Editorial note: publish numerical performance, memory and power specifications only when tied to an identifiable SKU and a primary source. Vendor-reported figures must be labeled as such.
Moore Threads develops full-function GPUs for graphics and AI (MTT S-series) with the MUSA software stack. The company completed a large STAR Market IPO in late 2025 amid China’s domestic GPU push, targeting intelligent-computing centers and PC/GPU markets.
Latest
- Shanghai trading debut — Dec 2025 — ~$1.1B STAR Market IPO; MTT S4000/S5000-class AI cards and MUSA stack in the domestic GPU wave.
MetaX (沐曦) ships C-series GPUs for training and inference with the MXMACA software stack for AI clusters and intelligent-computing centers. After listing on STAR in Dec 2025, the company reported strong revenue growth into 2026 as domestic GPU demand rose.
Latest
- MetaX doubles revenue — C500 mass production; C600 domestic-process follow-on; STAR 688802.SH (listed Dec 2025) with MXMACA for AI clusters.
Hygon’s Deep Computing Unit (DCU) accelerators are GPGPU-class chips widely used in China for large-model training and inference, paired with the DTK software stack. Hygon also ships x86 CPUs; the DCU line is the AI-relevant product for intelligent-computing centers.
Latest
- DeepSeek-V4 Day-0 adaptation — 2025–2026 — DCU + DTK widely used for LLM train/infer; same-day DeepSeek model adaptations reported with Ascend and Cambricon.
Iluvatar CoreX develops general-purpose GPU products for AI training and inference. Its public product portfolio spans the TianGai (天垓) training-GPU family, ZhiKai (智铠) inference products, and TongYang (彤央) edge-computing products. Product comparisons should be SKU-specific and distinguish announced roadmap items from shipping products.
Product families
- TianGai (天垓) — data-center GPU family for AI training and general-purpose acceleration; track generations such as BI-V-series by exact model and system availability.
- ZhiKai (智铠) — inference-oriented GPU products; record model support, precision, memory, and serving-engine integration separately from training products.
- TongYang (彤央) — edge-computing product family, distinct from the data-center training / inference portfolio.
Software ecosystem
- CoreX SDK — vendor development environment for programming, compiling, debugging, and deploying on CoreX accelerators.
- ixRT — inference runtime components; public source: iluvatar-corex-ixrt.
- IGIE / DeepSparkInference — inference engine and model deployment examples in the DeepSparkInference repository.
- DeepSpark — open-source ecosystem and model adaptation work: Deep-Spark GitHub organization.
Latest
- CoreX software platform — official software overview; use the vendor page for current SDK modules and supported product families.
- ixRT open-source components — inspect release tags, supported devices, framework dependencies, and CI before assigning production-support status.
Editorial note: upstream vLLM, SGLang, llama.cpp, and other serving support must be recorded per repository, release, device, and model. An example or community patch is not equivalent to full upstream support.
Enflame develops CloudBlazer (云燧) GCU accelerators and systems for data-center AI training and inference. Its portfolio includes separate training and inference product directions; system offerings and product availability should be distinguished from silicon announcements and roadmap claims.
Hardware and system direction
- CloudBlazer training products — track the T-series generations by exact SKU, supported server platform, memory configuration, and deployment status.
- Inference products — track the I-series and newer inference accelerators separately, including the target workload and software release.
- Multi-accelerator systems — record the number of GCU devices, interconnect topology, cooling and power envelope, and whether a system is announced, sampling, or deployed.
Software ecosystem: TopsRider
- TopsRuntime / TopsCompiler — execution and compilation components of the vendor platform.
- TopsAten — operator integration and PyTorch-facing functionality.
- ECCL — collective communication library for multi-GCU workloads.
- torch-gcu — public PyTorch extension: EnflameTechnology/torch-gcu. Its README documents PyTorch integration, AMP, profiling, GCU Graph, ECCL, `torch.compile`, and CUDA migration helpers; consult its current hardware / software compatibility table before deployment.
Latest
- torch-gcu open-source repository — a concrete public entry point for evaluating framework integration, version compatibility, examples, and CI evidence.
- Enflame official site — primary source for current CloudBlazer product and system announcements.
Editorial note: do not infer that every TopsRider component or serving framework supports every CloudBlazer SKU. Record the exact device and SDK release; distinguish public repository support from vendor-only deployment support.
Horizon Robotics (地平线) is a leading China automotive AI SoC vendor. Journey-series chips (through Journey 6 with BPU Nash) power L2+ assisted driving in many passenger vehicles, with increasing Transformer support for BEV/occupancy and end-to-end driving models.
Latest
- Journey 6 / BPU Nash — 2025–2026 — Journey 6 automotive AI SoCs with BPU Nash and stronger Transformer support widely designed into China passenger vehicles for L2+ ADAS.
Black Sesame Technologies (黑芝麻智能) designs automotive-grade ADAS/AD SoCs (Huashan family). Hong Kong-listed in 2024, the company focuses on safety-certified L2+/L3 platforms; A1000-family chips are reported in mass-production vehicles, with A2000 extending toward higher-performance and cross-domain AI.
Latest
- Huashan A1000 / A2000 path — 2025–2026 — A1000-family chips reported in mass-production L2+/L3 vehicles; A2000 messaging extends toward higher-performance and cross-domain AI inference.
The software landscape now spans graph compilers, kernel DSLs, operator libraries, inference runtimes, distributed serving, communication, and vendor SDKs. A flat compiler list no longer captures the real software stack.
- Compiler / IR: MLIR, OpenXLA / XLA, Apache TVM, IREE, TorchInductor.
- Kernel DSL: Triton, TileLang, TIRx, Helion, CuTe / CUTLASS DSL, JAX Pallas.
- Kernel / operator libraries: FlashAttention, FlashInfer, DeepGEMM, AITer, Composable Kernel.
- Serving: vLLM, SGLang, TensorRT-LLM, MLC-LLM, llama.cpp.
- Distributed serving / data movement: NVIDIA Dynamo, llm-d, Mooncake, NIXL, NCCL, RCCL.
- China vendor stacks: Huawei CANN, Cambricon Neuware, Hygon DTK, Biren BIRENSUPA, Iluvatar CoreX SDK / ixRT, Enflame TopsRider, Moore Threads MUSA, MetaX MXMACA.
Open the full Software Ecosystem guide → — includes layer-by-layer descriptions, public repositories, vendor integration notes, and a compatibility / maturity matrix.
Benchmark coverage should include model-level performance, serving latency, kernel efficiency, communication, memory, power, and cost. Results are comparable only when workload and measurement conditions are disclosed.
- Training / standardized inference: MLPerf / MLCommons.
- LLM serving: SemiAnalysis InferenceX, vLLM and SGLang benchmark tools.
- Kernel / operator: KernelBench, Triton / FlashInfer benchmark suites, CUTLASS profiler, Composable Kernel.
- Memory / interconnect: NCCL Tests, RCCL, OSU Micro-Benchmarks, STREAM.
- Power / cost: MLPerf Power, SPECpower, Green500, and transparent cost-per-token models.
Open the full Benchmark guide → — includes taxonomy, result schema, evidence classes, hardware coverage matrix, and methodology caveats.
Archive / background reading (not a current vendor list).
1. AI Chip Paper List2. Neural Network Accelerator Comparison (Tsinghua)
3. Tutorial on Hardware Architectures for Deep Neural Networks (MIT Eyeriss)
4. "What We Talk About When We Talk About AI Chip" — #1 · #2 · #3 · #4
5. TPU vs GPU vs Cerebras vs Graphcore (comparison essay)
6. "White Paper on AI Chip Technologies 2018" — download · Google Drive