arch/arm/stm32n6: Add STM32N6 chip and Nucleo-N657X0-Q board support

Documentation/platforms/arm/stm32n6/boards/nucleo-n657x0-q/index.rst

@@ -0,0 +1,172 @@
+==================
+ST Nucleo-N657X0-Q
+==================
+
+.. tags:: chip:stm32, chip:stm32n6, chip:stm32n657
+
+.. figure:: nucleo-n657x0-q.jpg
+   :width: 50 %
+   :align: center
+   :alt: STMicro Nucleo-N657X0-Q development board
+
+   Nucleo-N657X0-Q
+
+The STM Nucleo-N657X0-Q is a development
+board for the STM32N657X0H3Q, an Arm Cortex-M55 with 4 MiB of on-chip
+AXISRAM, an on-chip Neural-ART NPU, and no internal flash. In
+production, code is fetched from external XSPI NOR flash and in
+development, the image is loaded directly into AXISRAM by the on-board
+ST-LINK-V3EC. Refer to the
+https://www.st.com/en/evaluation-tools/nucleo-n657x0-q.html website
+for the full product page.
+
+Features
+========
+
+* STM32N657X0H3Q MCU (Arm Cortex-M55, up to 800 MHz)
+* On-chip Neural-ART NPU accelerator
+* 4 MiB on-chip AXISRAM (no internal flash)
+* External XSPI NOR flash interface
+* On-board ST-LINK-V3EC
+* 3 user LEDs (LD5 red, LD6 green, LD7 blue), plus status LEDs
+  (LD1 5V_PWR, LD4 PWR, LD9 COM)
+* User pushbutton (B1) and reset pushbutton
+* 32.768 kHz crystal oscillator
+* USB Type-C connectors (ST-LINK and user)
+* ST Zio connector
+* ST morpho headers
+
+.. warning::
+
+   This is the initial NuttX port for the STM32N6 family. The supported
+   peripheral set is intentionally minimal: USART1 (the ST-LINK VCOM
+   console), GPIO, RCC, PWR, and the SysTick-based timer. Other on-chip
+   peripherals and on-board features (XSPI flash boot, networking,
+   user LEDs/buttons, USB, MIPI, NPU, etc) are not yet wired up. The CPU is
+   currently clocked at 200 MHz from PLL1. Raising it to the standard
+   600 / 800 MHz operating points is deferred to a follow-up change.
+
+Buttons and LEDs
+================
+
+The board exposes three user LEDs and a user pushbutton, but the
+initial NuttX port does not yet ship ``userleds`` or ``buttons``
+drivers. The hardware wiring is summarised here so a follow-up
+driver can be written against an authoritative pin map:
+
+===== ======= ======== ======================================
+ID    Color   GPIO     Notes
+===== ======= ======== ======================================
+LD5   Red     PG10     Active low
+LD6   Green   PG0      Active low
+LD7   Blue    PG8      Active low
+B1    Blue    PC13     Active high, external pull-down
+===== ======= ======== ======================================
+
+Pin Mapping
+===========
+
+The shipped configurations map only the pins required for the serial
+console. All other GPIOs retain their reset state and are free for
+application use.
+
+===== ============= ======= =================================
+Pin   Signal        AF      Notes
+===== ============= ======= =================================
+PE5   USART1_TX     AF7     Routed to ST-LINK VCOM (host RX)
+PE6   USART1_RX     AF7     Routed to ST-LINK VCOM (host TX)
+===== ============= ======= =================================
+
+Power Supply
+============
+
+The board is powered over either USB Type-C connector (ST-LINK or
+user) at 5 V. On-board regulators derive the MCU and I/O rails. See
+the ST user manual for the full power tree and jumper selection.
+
+Installation
+============
+
+Two host tools are required:
+
+* A bare-metal Arm toolchain, e.g. the GNU Arm Embedded toolchain
+  (``arm-none-eabi-gcc``) packaged by most Linux distributions or
+  available from Arm.
+* `STM32CubeProgrammer
+  <https://www.st.com/en/development-tools/stm32cubeprog.html>`_ for
+  loading images into AXISRAM over the on-board ST-LINK.
+
+Building NuttX
+==============
+
+From the top of the NuttX source tree:
+
+.. code:: console
+
+   $ ./tools/configure.sh nucleo-n657x0-q:<config>
+   $ make
+
+At the end of the build, ``nuttx.bin`` is the raw image that the
+flashing step below loads into AXISRAM.
+
+The toolchain selection can be changed via ``make menuconfig``.
+
+Flashing
+========
+
+The board boots in development mode: the on-board ST-LINK loads the
+image directly into AXISRAM at ``0x34000400`` (the first 1 KiB is
+reserved for the boot ROM header) and starts execution there. Signed
+XSPI flash boot via a first-stage bootloader is not yet supported.
+
+Use STM32CubeProgrammer's CLI to load and run ``nuttx.bin``:
+
+.. code:: console
+
+   $ STM32_Programmer_CLI -c port=SWD mode=UR -halt              \
+         -d nuttx.bin 0x34000400                                 \
+         -w32 0xE000ED08 0x34000400                              \
+         -g 0x34000400
+
+The ``-w32`` write retargets VTOR to the SRAM image before the ``-g``
+jump, so the Cortex-M55 starts from the NuttX vector table rather
+than the boot ROM's.
+
+Configurations
+==============
+
+Each configuration is selected with::
+
+   $ ./tools/configure.sh nucleo-n657x0-q:<config>
+
+Unless otherwise noted, console output is accessed via ST-LINK
+(USART1) at 115200 8N1.
+
+nsh
+---
+
+Minimal NuttShell configuration. Boots into the NSH prompt via
+ST-LINK and exposes the built-in commands plus
+:doc:`getprime </applications/testing/getprime/index>`-style apps
+selectable via ``make menuconfig``.
+
+ostest
+------
+
+Builds the NSH configuration with :doc:`apps/testing/ostest
+</applications/testing/ostest/index>` added. Run ``ostest`` from the
+NSH prompt to exercise the core RTOS primitives (tasks, mutexes,
+semaphores, signals, message queues, POSIX timers, condition
+variables, scheduling). Used as the smoke test.
+
+License Exceptions
+==================
+
+None.
+
+References
+==========
+
+* [RM0486] STM32N647/657xx Arm\ :sup:`®`-based 32-bit MCUs reference manual
+* [UM3417] STM32N6 Nucleo-144 board (MB1940) user manual
+* [ES0620] STM32N657 errata sheet

Documentation/platforms/arm/stm32n6/index.rst

@@ -0,0 +1,71 @@
+==========
+ST STM32N6
+==========
+
+This is a port of NuttX to the STM32N6 family.
+The STM32N6 is a chip based on the Arm Cortex-M55.
+
+Development is performed on the Nucleo-N657X0-Q.  At this time only the
+STM32N657X0 is supported.  Kconfig will need updates to support other
+MCUs in the family.
+
+Supported MCUs
+==============
+
+===========  ======= ================
+MCU          Support Note
+===========  ======= ================
+STM32N645     No
+STM32N647     No
+STM32N655     No
+STM32N657     Yes    STM32N657X0 only
+===========  ======= ================
+
+Peripheral Support
+==================
+
+The following list indicates peripherals supported in NuttX:
+
+==========  =======  ===============================================
+Peripheral  Support  Notes
+==========  =======  ===============================================
+GPIO        Yes
+PWR         Yes      Partial.
+RCC         Yes      PLL1 clock tree.
+USART       Yes      USART1 only.
+
+ADC         No
+DCACHE      No
+DCMIPP      No
+DMA         No
+ETH         No
+I2C         No
+ICACHE      No
+IWDG        No
+LPTIM       No
+LTDC        No
+MPU         No
+NPU         No
+RNG         No
+RTC         No
+SAI         No
+SDMMC       No
+SPI         No
+TIM         No
+USB         No
+XSPI        No
+==========  =======  ===============================================
+
+References
+==========
+
+[RM0486] STMicroelectronics, STM32N647/657xx Arm®-based 32-bit MCUs
+
+Supported Boards
+================
+
+.. toctree::
+   :glob:
+   :maxdepth: 1
+
+   boards/*/*

arch/arm/Kconfig

@@ -587,6 +587,19 @@ config ARCH_CHIP_STM32H5
 	---help---
 		STMicro STM32 H5 architectures (ARM Cortex-M33).
 
+config ARCH_CHIP_STM32N6
+	bool "STMicro STM32 N6"
+	select ARCH_CORTEXM55
+	select ARCH_HAVE_FPU
+	select ARCH_HAVE_MPU
+	select ARM_HAVE_DSP
+	select ARM_HAVE_MPU_UNIFIED
+	select ARCH_HAVE_TRUSTZONE
+	select ARCH_HAVE_FETCHADD
+	select ARCH_HAVE_HEAPCHECK
+	---help---
+		STMicro STM32N6 architectures (ARM Cortex-M55).
+
 config ARCH_CHIP_STM32L5
 	bool "STMicro STM32 L5"
 	select ARCH_CORTEXM33
@@ -1199,6 +1212,7 @@ config ARCH_CHIP
 	default "stm32h7"	if ARCH_CHIP_STM32H7
 	default "stm32l4"	if ARCH_CHIP_STM32L4
 	default "stm32h5"	if ARCH_CHIP_STM32H5
+	default "stm32n6"	if ARCH_CHIP_STM32N6
 	default "stm32l5"	if ARCH_CHIP_STM32L5
 	default "stm32u5"	if ARCH_CHIP_STM32U5
 	default "stm32wb"	if ARCH_CHIP_STM32WB
@@ -1709,6 +1723,9 @@ endif
 if ARCH_CHIP_STM32H5
 source "arch/arm/src/stm32h5/Kconfig"
 endif
+if ARCH_CHIP_STM32N6
+source "arch/arm/src/stm32n6/Kconfig"
+endif
 if ARCH_CHIP_STM32L5
 source "arch/arm/src/stm32l5/Kconfig"
 endif

arch/arm/include/stm32n6/chip.h

@@ -0,0 +1,69 @@
+/****************************************************************************
+ * arch/arm/include/stm32n6/chip.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_STM32N6_CHIP_H
+#define __ARCH_ARM_INCLUDE_STM32N6_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/* Memory sizes - STM32N6 has no internal flash.  Code runs from the
+ * on-chip AXI SRAM (loaded by the debugger in DEV mode, or by an FSBL
+ * from external XSPI flash in normal boot).
+ *
+ * AXI SRAM layout (from CMSIS stm32n657xx.h):
+ *   AXISRAM1:     0x34000000  1 MB
+ *   AXISRAM2:     0x34100000  1 MB
+ *   AXISRAM3:     0x34200000  448 KB
+ *   AXISRAM4:     0x34270000  448 KB
+ *   AXISRAM5:     0x342E0000  448 KB
+ *   AXISRAM6:     0x34350000  448 KB
+ *   CACHEAXIRAM:  0x343C0000  256 KB
+ *   -------------------------------------------
+ *   Total:                    4 MB    (end = 0x34400000)
+ *
+ * VENCRAM (128 KB at 0x34400000) is excluded -- reserved for video encoder.
+ * Each bank requires its RCC MEMENR clock enable bit to be set.
+ */
+
+#define STM32N6_SRAM_SIZE         (4 * 1024 * 1024)  /* 4194304 bytes (4 MiB) */
+
+#define STM32N6_NPORTS                  (12)   /* GPIO ports A-H (8) + N, O, P, Q (4) */
+#define STM32N6_NUSART                   (1)   /* USART1 */
+
+/* NVIC priority levels *****************************************************/
+
+/* 16 Programmable interrupt levels (4-bit priority) */
+
+#define NVIC_SYSH_PRIORITY_MIN     0xf0 /* All bits set in minimum priority */
+#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
+#define NVIC_SYSH_PRIORITY_MAX     0x00 /* Zero is maximum priority */
+#define NVIC_SYSH_PRIORITY_STEP    0x10 /* Four bits of interrupt priority used */
+
+#endif /* __ARCH_ARM_INCLUDE_STM32N6_CHIP_H */