ch32 USBHD/USBHS driver implementation

core/src/core/usb.zig

@@ -274,7 +274,7 @@ pub fn DeviceController(config: Config, driver_args: config.DriverArgs()) type {
             const desc_device: descriptor.Device = .{
                 .bcd_usb = config.bcd_usb,
                 .device_triple = config.device_triple,
-                .max_packet_size0 = @max(config.max_supported_packet_size, 64),
+                .max_packet_size0 = @min(config.max_supported_packet_size, 64),
                 .vendor = .from(config.vendor.id),
                 .product = .from(config.product.id),
                 .bcd_device = config.bcd_device,

examples/wch/ch32v/build.zig

@@ -53,6 +53,7 @@ pub fn build(b: *std.Build) void {
         .{ .target = mb.ports.ch32v.chips.ch32v303xb, .name = "blinky_systick_ch32v303", .file = "src/blinky_systick.zig" },
         .{ .target = mb.ports.ch32v.boards.ch32v305.nano_ch32v305, .name = "nano_ch32v305_blinky", .file = "src/board_blinky.zig" },
         .{ .target = mb.ports.ch32v.boards.ch32v307.ch32v307v_r1_1v0, .name = "ch32v307v_r1_1v0_blinky", .file = "src/blinky.zig" },
+        .{ .target = mb.ports.ch32v.boards.ch32v307.ch32v307v_r1_1v0, .name = "ch32v307v_r1_1v0_usb_cdc", .file = "src/usb_cdc.zig" },
     };
 
     for (available_examples) |example| {

examples/wch/ch32v/src/usb_cdc.zig

@@ -0,0 +1,134 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+const hal = microzig.hal;
+const time = hal.time;
+const gpio = hal.gpio;
+const usb = microzig.core.usb;
+
+const USB_Serial = usb.drivers.CDC;
+
+const RCC = microzig.chip.peripherals.RCC;
+const AFIO = microzig.chip.peripherals.AFIO;
+const PFIC = microzig.chip.peripherals.PFIC;
+
+const usart = hal.usart.instance.USART1;
+
+const usart_tx_pin = gpio.Pin.init(0, 9); // PA9
+
+pub const microzig_options = microzig.Options{
+    .logFn = hal.usart.log,
+    .log_level = .debug,
+    .log_scope_levels = &.{
+        .{ .scope = .usb_dev, .level = .warn },
+        .{ .scope = .usb_ctrl, .level = .warn },
+        .{ .scope = .usb_cdc, .level = .warn },
+    },
+};
+
+const USBController = usb.DeviceController(.{
+    .bcd_usb = .v2_00,
+    .device_triple = .unspecified,
+    .vendor = .{ .id = 0x2E8A, .str = "MicroZig" },
+    .product = .{ .id = 0x000A, .str = "ch32v307 Test Device" },
+    .bcd_device = .v1_00,
+    .serial = "someserial",
+    .max_supported_packet_size = 512,
+    .configurations = &.{.{
+        .attributes = .{ .self_powered = false },
+        .max_current_ma = 50,
+        .Drivers = struct { serial: USB_Serial },
+    }},
+}, .{.{
+    .serial = .{ .itf_notifi = "Board CDC", .itf_data = "Board CDC Data" },
+}});
+
+pub var usb_dev: hal.usbhs.Polled(
+    .{ .prefer_high_speed = true },
+) = undefined;
+
+var usb_controller: USBController = .init;
+
+pub fn main() !void {
+    // Board brings up clocks and time
+    microzig.board.init();
+    microzig.hal.init();
+
+    // Enable peripheral clocks for USART1 and GPIOA
+    RCC.APB2PCENR.modify(.{
+        .IOPAEN = 1, // Enable GPIOA clock
+        .AFIOEN = 1, // Enable AFIO clock
+        .USART1EN = 1, // Enable USART1 clock
+    });
+
+    // Configure TX pin as alternate function push-pull
+    usart_tx_pin.set_output_mode(.alternate_function_push_pull, .max_50MHz);
+
+    // Initialize USART1 at 115200 baud
+    usart.apply(.{ .baud_rate = 115200 });
+
+    hal.usart.init_logger(usart);
+    std.log.info("UART logging initialized.", .{});
+
+    std.log.info("Initializing USB device.", .{});
+
+    usb_dev = .init();
+
+    var i: u32 = 0;
+    var old: u64 = time.get_time_since_boot().to_us();
+    var new: u64 = 0;
+
+    while (true) {
+        if (usb_controller.drivers()) |drivers| {
+            new = time.get_time_since_boot().to_us();
+            if (new - old > 500000) {
+                old = new;
+                i += 1;
+                std.log.info("cdc test: {}", .{i});
+
+                usb_cdc_write(&drivers.serial, "This is very very very very very very very very long text sent from ch32v30x by USB CDC to your device: {}\r\n", .{i});
+            }
+
+            // read and print host command if present
+            const message = usb_cdc_read(&drivers.serial);
+            if (message.len > 0) {
+                usb_cdc_write(&drivers.serial, "Your message to me was: {s}\r\n", .{message});
+            }
+        }
+        usb_dev.poll(false, &usb_controller);
+    }
+}
+
+var usb_tx_buff: [1024]u8 = undefined;
+
+// Transfer data to host
+// NOTE: After each USB chunk transfer, we have to call the USB task so that bus TX events can be handled
+pub fn usb_cdc_write(serial: *USB_Serial, comptime fmt: []const u8, args: anytype) void {
+    const text = std.fmt.bufPrint(&usb_tx_buff, fmt, args) catch &.{};
+    var write_buff = text;
+    while (write_buff.len > 0) {
+        write_buff = write_buff[serial.write(write_buff)..];
+        while (!serial.flush())
+            usb_dev.poll(false, &usb_controller);
+    }
+}
+
+var usb_rx_buff: [1024]u8 = undefined;
+
+// Receive data from host
+// NOTE: Read code was not tested extensively. In case of issues, try to call USB task before every read operation
+pub fn usb_cdc_read(
+    serial: *USB_Serial,
+) []const u8 {
+    var total_read: usize = 0;
+    var read_buff: []u8 = usb_rx_buff[0..];
+
+    while (true) {
+        const len = serial.read(read_buff);
+        read_buff = read_buff[len..];
+        total_read += len;
+        if (len == 0) break;
+    }
+
+    return usb_rx_buff[0..total_read];
+}

port/wch/ch32v/src/boards/CH32V307V-R1-1v0.zig

@@ -6,7 +6,8 @@ const ch32v = microzig.hal;
 
 /// Clock configuration for this board
 pub const clock_config: ch32v.clocks.Config = .{
-    .source = .hsi,
+    .source = .hse,
+    .hse_frequency = 8_000_000,
     .target_frequency = 48_000_000,
 };
 

port/wch/ch32v/src/hals/ch32v30x.zig

@@ -5,18 +5,31 @@ pub const clocks = @import("clocks.zig");
 pub const time = @import("time.zig");
 pub const i2c = @import("i2c.zig");
 pub const usart = @import("usart.zig");
+const std = @import("std");
+pub const usbhs = @import("./usbhs.zig");
 
 /// HSI (High Speed Internal) oscillator frequency
 /// This is the fixed internal RC oscillator frequency for CH32V30x
 pub const hsi_frequency: u32 = 8_000_000; // 8 MHz
+pub const hse_frequency: u32 = 8_000_000; // 8 MHz
 
 /// Default interrupt handlers provided by the HAL
 pub const default_interrupts: microzig.cpu.InterruptOptions = .{
     .TIM2 = time.tim2_handler,
+    // .USBHS = usb.usbhs_interrupt_handler,
 };
 
 /// Initialize HAL subsystems used by default
 pub fn init() void {
     // Configure TIM2 timing driver
     time.init();
+    clocks.init(.{
+        .source = .hse,
+        .hse_frequency = hse_frequency,
+        .target_frequency = 48_000_000,
+    }); // 8 MHz external crystal
+    clocks.enable_usbhs_clock(.{
+        .ref_source_hz = hse_frequency,
+        .ref_source = .hse,
+    });
 }

port/wch/ch32v/src/hals/clocks.zig

@@ -413,6 +413,150 @@ pub fn get_freqs() ClockSpeeds {
     };
 }
 
+// ============================================================================
+// Enable + configure USBHS clocks.
+// ============================================================================
+
+/// This configures RCC_CFGR2 fields for the USBHS PHY PLL reference (if present),
+/// selects whether the USBHS 48MHz clock comes from the system PLL clock or the USB PHY,
+/// and enables the AHB clock gate for USBHS.
+///
+/// Note: The SVD names bit31 as `USBFSSRC`, but the reference manual
+/// describes it as `USBHSSRC` ("USBHS 48MHz clock source selection").
+pub const UsbHsClockConfig = struct {
+    pub const RefSource = enum { hse, hsi };
+    /// Desired PHY PLL reference frequency (the USBHSCLK field selects one of these).
+    /// If null, we'll pick the highest one we can generate exactly: 8MHz, then 5MHz, 4MHz, 3MHz.
+    pub const RefFreq = enum(u2) {
+        mhz3 = 0b00,
+        mhz4 = 0b01,
+        mhz8 = 0b10,
+        mhz5 = 0b11,
+    };
+
+    /// If true select USB PHY as the 48MHz source and enable the PHY internal PLL.
+    /// If false, select PLL CLK as the 48MHz source (you must ensure a valid 48MHz PLL clock exists).
+    use_phy_48mhz: bool = true,
+
+    /// PHY PLL reference source (only used when use_phy_48mhz).
+    ref_source: RefSource = .hse,
+
+    /// Frequency of the chosen ref_source, in Hz.
+    /// Typical: HSE crystal (e.g. 8_000_000, 12_000_000, 24_000_000) or HSI (often 8_000_000).
+    ref_source_hz: u32,
+
+    ref_freq: ?RefFreq = null,
+};
+
+fn div_to_usbhsdiv(div: u32) u3 {
+    // RCC_CFGR2 USBHSDIV encoding:
+    // 000: /1, 001: /2, ... 111: /8
+    return @as(u3, @intCast(div - 1));
+}
+
+fn hz_for_ref(ref: UsbHsClockConfig.RefFreq) u32 {
+    return switch (ref) {
+        .mhz3 => 3_000_000,
+        .mhz4 => 4_000_000,
+        .mhz5 => 5_000_000,
+        .mhz8 => 8_000_000,
+    };
+}
+
+const HSPLLSRC = enum(u2) {
+    hse = 0,
+    hsi = 1,
+};
+
+/// Selects USBHS Clock source, options are:
+/// - "PLL CLK" 48MHz source (cfg.use_phy_48mhz = false), or
+/// - "USB PHY" 48MHz source (cfg.use_phy_48mhz = true),
+///   in which case it also configures the PHY PLL reference (USBHSCLK/USBHSPLLSRC/USBHSDIV)
+///   and enables the PHY internal PLL (USBHSPLL).
+pub fn enable_usbhs_clock(comptime cfg: UsbHsClockConfig) void {
+    // Turn on the AHB clock gate for the USBHS peripheral block.
+
+    // If caller prefers PLL CLK, set PLL CLK selection and keep PHY PLL off.
+    if (!cfg.use_phy_48mhz) {
+        RCC.CFGR2.modify(.{
+            // SVD name mismatch: USBFSSRC field == USBHS 48MHz source select per RM.
+            .USBFSSRC = 0, // 0: PLL CLK
+            .USBHSPLL = 0, // PHY internal PLL disabled
+        });
+        return;
+    }
+
+    // Ensure the selected oscillator is on (best-effort; usually already enabled by system clock init).
+    switch (cfg.ref_source) {
+        .hse => {
+            if (RCC.CTLR.read().HSEON == 0) RCC.CTLR.modify(.{ .HSEON = 1 });
+            while (RCC.CTLR.read().HSERDY == 0) {}
+        },
+        .hsi => {
+            if (RCC.CTLR.read().HSION == 0) RCC.CTLR.modify(.{ .HSION = 1 });
+            while (RCC.CTLR.read().HSIRDY == 0) {}
+        },
+    }
+
+    // Choose a reference frequency and divider that is exactly achievable.
+    const candidates = [_]UsbHsClockConfig.RefFreq{ .mhz8, .mhz5, .mhz4, .mhz3 };
+
+    comptime var chosen_ref: UsbHsClockConfig.RefFreq = undefined;
+    comptime var chosen_div: u32 = 0;
+    comptime {
+        if (cfg.ref_freq) |forced| {
+            const want = hz_for_ref(forced);
+            var found = false;
+            for (1..9) |div| {
+                if (cfg.ref_source_hz % div == 0 and (cfg.ref_source_hz / div) == want) {
+                    chosen_ref = forced;
+                    chosen_div = div;
+                    found = true;
+                    break;
+                }
+            }
+            if (!found) {
+                @compileError("USBHS PHY PLL ref cannot be generated exactly from ref_source_hz with /1..8 prescaler.");
+            }
+        } else {
+            var found = false;
+            for (candidates) |ref| {
+                const want = hz_for_ref(ref);
+                for (1..9) |div| {
+                    if (cfg.ref_source_hz % div == 0 and (cfg.ref_source_hz / div) == want) {
+                        chosen_ref = ref;
+                        chosen_div = div;
+                        found = true;
+                        break;
+                    }
+                }
+                if (found) break;
+            }
+            if (!found) {
+                @compileError("USBHS PHY PLL ref cannot be generated: need 3/4/5/8MHz from ref_source_hz using /1..8 prescaler.");
+            }
+        }
+    }
+    // Program CFGR2:
+    // - USBHSPLLSRC: 0=HSE, 1=HSI
+    // - USBHSDIV: prescaler (/1..8)
+    // - USBHSCLK: selects which ref freq the PHY PLL expects (3/4/8/5 MHz)
+    // - USBHSPLL: enable PHY internal PLL
+    // - USBHSSRC (SVD calls it USBFSSRC): 1=USB PHY as 48MHz source
+    RCC.CFGR2.modify(.{
+        .USBHSPLLSRC = switch (cfg.ref_source) {
+            .hse => 0,
+            .hsi => 1,
+        },
+        .USBHSDIV = div_to_usbhsdiv(chosen_div),
+        .USBHSCLK = @as(u2, @intFromEnum(chosen_ref)),
+        .USBHSPLL = 1,
+        .USBFSSRC = 1, // RM: USBHS 48MHz clock source = USB PHY
+    });
+
+    RCC.AHBPCENR.modify(.{ .USBHS_EN = 1 });
+}
+
 // ============================================================================
 // Convenience Functions for HAL Modules
 // ============================================================================