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[spec] Fix input shape for relaxed_dot_add #2250

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Merged
rossberg merged 1 commit into from
Sep 21, 2026
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[spec] Fix input shape for relaxed_dot_add #2250

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2 changes: 1 addition & 1 deletion specification/wasm-3.0/5.3-binary.instructions.spectec
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Expand Up @@ -679,7 +679,7 @@ grammar Binstr/vec-extbin-i32x4 : instr = ...
| ...

grammar Binstr/vec-exttern-i32x4 : instr = ...
| 0xFD 275:Bu32 => VEXTTERNOP (I32 X `4) (I16 X `8) RELAXED_DOT_ADD S
| 0xFD 275:Bu32 => VEXTTERNOP (I32 X `4) (I8 X `16) RELAXED_DOT_ADD S
| ...

grammar Binstr/vec-un-i64x2 : instr = ...
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2 changes: 1 addition & 1 deletion specification/wasm-3.0/6.3-text.instructions.spectec
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Expand Up @@ -1003,7 +1003,7 @@ grammar Tplaininstr_(I)/vec-extbin-i64x2 : instr = ...
| ...

grammar Tplaininstr_(I)/vec-exttern-i32x4 : instr = ...
| "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP (I32 X `4) (I16 X `8) RELAXED_DOT_ADD S
| "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP (I32 X `4) (I8 X `16) RELAXED_DOT_ADD S


;; Expressions
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2 changes: 1 addition & 1 deletion specification/wasm-latest/5.3-binary.instructions.spectec
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Expand Up @@ -679,7 +679,7 @@ grammar Binstr/vec-extbin-i32x4 : instr = ...
| ...

grammar Binstr/vec-exttern-i32x4 : instr = ...
| 0xFD 275:Bu32 => VEXTTERNOP (I32 X `4) (I16 X `8) RELAXED_DOT_ADD S
| 0xFD 275:Bu32 => VEXTTERNOP (I32 X `4) (I8 X `16) RELAXED_DOT_ADD S
| ...

grammar Binstr/vec-un-i64x2 : instr = ...
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2 changes: 1 addition & 1 deletion specification/wasm-latest/6.3-text.instructions.spectec
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Expand Up @@ -1003,7 +1003,7 @@ grammar Tplaininstr_(I)/vec-extbin-i64x2 : instr = ...
| ...

grammar Tplaininstr_(I)/vec-exttern-i32x4 : instr = ...
| "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP (I32 X `4) (I16 X `8) RELAXED_DOT_ADD S
| "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP (I32 X `4) (I8 X `16) RELAXED_DOT_ADD S


;; Expressions
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4 changes: 2 additions & 2 deletions spectec/test-frontend/TEST.md
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Expand Up @@ -9921,7 +9921,7 @@ grammar Binstr : instr
;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:678.5-678.67
prod {{0xFD} {`%`_u32(191,):Bu32}} => VEXTBINOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), EXTMUL_vextbinop__(HIGH_half, U_sx))
;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:682.5-682.72
prod {{0xFD} {`%`_u32(275,):Bu32}} => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), RELAXED_DOT_ADDS_vextternop__)
prod {{0xFD} {`%`_u32(275,):Bu32}} => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I8_lanetype, `%`_dim(16,)),), RELAXED_DOT_ADDS_vextternop__)
;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:686.5-686.42
prod {{0xFD} {`%`_u32(192,):Bu32}} => VUNOP_instr(`%X%`_shape(I64_lanetype, `%`_dim(2,)), ABS_vunop_)
;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:687.5-687.42
Expand Down Expand Up @@ -12081,7 +12081,7 @@ grammar Tplaininstr_(I : I) : instr
;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec
prod "i64x2.extmul_high_i32x4_u" => VEXTBINOP_instr(`%`_ishape(`%X%`_shape(I64_lanetype, `%`_dim(2,)),), `%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), EXTMUL_vextbinop__(HIGH_half, U_sx))
;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec
prod "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), RELAXED_DOT_ADDS_vextternop__)
prod "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I8_lanetype, `%`_dim(16,)),), RELAXED_DOT_ADDS_vextternop__)

;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec
rec {
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4 changes: 2 additions & 2 deletions spectec/test-latex/TEST.md
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Expand Up @@ -12105,7 +12105,7 @@ $$
& & | & \mathtt{0xFD}~~189{:}{\mathtt{u32}} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 32}}}{\mathsf{x}}{\mathsf{{\scriptstyle 4}}} {.} {{\mathsf{extmul}}{\mathsf{\_}}{\mathsf{high}}{\mathsf{\_}}{\mathsf{s}}}{\mathsf{\_}}{{\mathsf{i{\scriptstyle 16}}}{\mathsf{x}}{\mathsf{{\scriptstyle 8}}}} \\
& & | & \mathtt{0xFD}~~190{:}{\mathtt{u32}} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 32}}}{\mathsf{x}}{\mathsf{{\scriptstyle 4}}} {.} {{\mathsf{extmul}}{\mathsf{\_}}{\mathsf{low}}{\mathsf{\_}}{\mathsf{u}}}{\mathsf{\_}}{{\mathsf{i{\scriptstyle 16}}}{\mathsf{x}}{\mathsf{{\scriptstyle 8}}}} \\
& & | & \mathtt{0xFD}~~191{:}{\mathtt{u32}} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 32}}}{\mathsf{x}}{\mathsf{{\scriptstyle 4}}} {.} {{\mathsf{extmul}}{\mathsf{\_}}{\mathsf{high}}{\mathsf{\_}}{\mathsf{u}}}{\mathsf{\_}}{{\mathsf{i{\scriptstyle 16}}}{\mathsf{x}}{\mathsf{{\scriptstyle 8}}}} \\
& & | & \mathtt{0xFD}~~275{:}{\mathtt{u32}} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 32}}}{\mathsf{x}}{\mathsf{{\scriptstyle 4}}} {.} {{\mathsf{relaxed\_dot\_add}}{\mathsf{\_}}{\mathsf{s}}}{\mathsf{\_}}{{\mathsf{i{\scriptstyle 16}}}{\mathsf{x}}{\mathsf{{\scriptstyle 8}}}} \\
& & | & \mathtt{0xFD}~~275{:}{\mathtt{u32}} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 32}}}{\mathsf{x}}{\mathsf{{\scriptstyle 4}}} {.} {{\mathsf{relaxed\_dot\_add}}{\mathsf{\_}}{\mathsf{s}}}{\mathsf{\_}}{{\mathsf{i{\scriptstyle 8}}}{\mathsf{x}}{\mathsf{{\scriptstyle 16}}}} \\
& & | & \mathtt{0xFD}~~192{:}{\mathtt{u32}} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 64}}}{\mathsf{x}}{\mathsf{{\scriptstyle 2}}} {.} \mathsf{abs} \\
& & | & \mathtt{0xFD}~~193{:}{\mathtt{u32}} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 64}}}{\mathsf{x}}{\mathsf{{\scriptstyle 2}}} {.} \mathsf{neg} \\
& & | & \mathtt{0xFD}~~195{:}{\mathtt{u32}} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 64}}}{\mathsf{x}}{\mathsf{{\scriptstyle 2}}} {.} \mathsf{all\_true} \\
Expand Down Expand Up @@ -13616,7 +13616,7 @@ $$
& & | & \mbox{‘\texttt{i64x2.extmul\_low\_i32x4\_u}’} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 64}}}{\mathsf{x}}{\mathsf{{\scriptstyle 2}}} {.} {{\mathsf{extmul}}{\mathsf{\_}}{\mathsf{low}}{\mathsf{\_}}{\mathsf{u}}}{\mathsf{\_}}{{\mathsf{i{\scriptstyle 32}}}{\mathsf{x}}{\mathsf{{\scriptstyle 4}}}} \\
& & | & \mbox{‘\texttt{i64x2.extmul\_high\_i32x4\_s}’} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 64}}}{\mathsf{x}}{\mathsf{{\scriptstyle 2}}} {.} {{\mathsf{extmul}}{\mathsf{\_}}{\mathsf{high}}{\mathsf{\_}}{\mathsf{s}}}{\mathsf{\_}}{{\mathsf{i{\scriptstyle 32}}}{\mathsf{x}}{\mathsf{{\scriptstyle 4}}}} \\
& & | & \mbox{‘\texttt{i64x2.extmul\_high\_i32x4\_u}’} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 64}}}{\mathsf{x}}{\mathsf{{\scriptstyle 2}}} {.} {{\mathsf{extmul}}{\mathsf{\_}}{\mathsf{high}}{\mathsf{\_}}{\mathsf{u}}}{\mathsf{\_}}{{\mathsf{i{\scriptstyle 32}}}{\mathsf{x}}{\mathsf{{\scriptstyle 4}}}} \\
& & | & \mbox{‘\texttt{i32x4.relaxed\_dot\_i8x16\_i7x16\_add\_s}’} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 32}}}{\mathsf{x}}{\mathsf{{\scriptstyle 4}}} {.} {{\mathsf{relaxed\_dot\_add}}{\mathsf{\_}}{\mathsf{s}}}{\mathsf{\_}}{{\mathsf{i{\scriptstyle 16}}}{\mathsf{x}}{\mathsf{{\scriptstyle 8}}}} \\
& & | & \mbox{‘\texttt{i32x4.relaxed\_dot\_i8x16\_i7x16\_add\_s}’} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 32}}}{\mathsf{x}}{\mathsf{{\scriptstyle 4}}} {.} {{\mathsf{relaxed\_dot\_add}}{\mathsf{\_}}{\mathsf{s}}}{\mathsf{\_}}{{\mathsf{i{\scriptstyle 8}}}{\mathsf{x}}{\mathsf{{\scriptstyle 16}}}} \\
\end{array}
$$

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12 changes: 6 additions & 6 deletions spectec/test-middlend/TEST.md
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Expand Up @@ -9444,7 +9444,7 @@ grammar Binstr : instr
;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:678.5-678.67
prod {{0xFD} {`%`_u32(191,):Bu32}} => VEXTBINOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), EXTMUL_vextbinop__(HIGH_half, U_sx))
;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:682.5-682.72
prod {{0xFD} {`%`_u32(275,):Bu32}} => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), RELAXED_DOT_ADDS_vextternop__)
prod {{0xFD} {`%`_u32(275,):Bu32}} => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I8_lanetype, `%`_dim(16,)),), RELAXED_DOT_ADDS_vextternop__)
;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:686.5-686.42
prod {{0xFD} {`%`_u32(192,):Bu32}} => VUNOP_instr(`%X%`_shape(I64_lanetype, `%`_dim(2,)), ABS_vunop_)
;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:687.5-687.42
Expand Down Expand Up @@ -11604,7 +11604,7 @@ grammar Tplaininstr_(I : I) : instr
;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec
prod "i64x2.extmul_high_i32x4_u" => VEXTBINOP_instr(`%`_ishape(`%X%`_shape(I64_lanetype, `%`_dim(2,)),), `%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), EXTMUL_vextbinop__(HIGH_half, U_sx))
;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec
prod "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), RELAXED_DOT_ADDS_vextternop__)
prod "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I8_lanetype, `%`_dim(16,)),), RELAXED_DOT_ADDS_vextternop__)

;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec
rec {
Expand Down Expand Up @@ -21355,7 +21355,7 @@ grammar Binstr : instr
;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:678.5-678.67
prod {{0xFD} {`%`_u32(191,):Bu32}} => VEXTBINOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), EXTMUL_vextbinop__(HIGH_half, U_sx))
;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:682.5-682.72
prod {{0xFD} {`%`_u32(275,):Bu32}} => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), RELAXED_DOT_ADDS_vextternop__)
prod {{0xFD} {`%`_u32(275,):Bu32}} => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I8_lanetype, `%`_dim(16,)),), RELAXED_DOT_ADDS_vextternop__)
;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:686.5-686.42
prod {{0xFD} {`%`_u32(192,):Bu32}} => VUNOP_instr(`%X%`_shape(I64_lanetype, `%`_dim(2,)), ABS_vunop_)
;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:687.5-687.42
Expand Down Expand Up @@ -23515,7 +23515,7 @@ grammar Tplaininstr_(I : I) : instr
;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec
prod "i64x2.extmul_high_i32x4_u" => VEXTBINOP_instr(`%`_ishape(`%X%`_shape(I64_lanetype, `%`_dim(2,)),), `%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), EXTMUL_vextbinop__(HIGH_half, U_sx))
;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec
prod "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), RELAXED_DOT_ADDS_vextternop__)
prod "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I8_lanetype, `%`_dim(16,)),), RELAXED_DOT_ADDS_vextternop__)

;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec
rec {
Expand Down Expand Up @@ -33508,7 +33508,7 @@ grammar Binstr : instr
;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:678.5-678.67
prod {{0xFD} {`%`_u32(191,):Bu32}} => VEXTBINOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), EXTMUL_vextbinop__(HIGH_half, U_sx))
;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:682.5-682.72
prod {{0xFD} {`%`_u32(275,):Bu32}} => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), RELAXED_DOT_ADDS_vextternop__)
prod {{0xFD} {`%`_u32(275,):Bu32}} => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I8_lanetype, `%`_dim(16,)),), RELAXED_DOT_ADDS_vextternop__)
;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:686.5-686.42
prod {{0xFD} {`%`_u32(192,):Bu32}} => VUNOP_instr(`%X%`_shape(I64_lanetype, `%`_dim(2,)), ABS_vunop_)
;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:687.5-687.42
Expand Down Expand Up @@ -35668,7 +35668,7 @@ grammar Tplaininstr_(I : I) : instr
;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec
prod "i64x2.extmul_high_i32x4_u" => VEXTBINOP_instr(`%`_ishape(`%X%`_shape(I64_lanetype, `%`_dim(2,)),), `%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), EXTMUL_vextbinop__(HIGH_half, U_sx))
;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec
prod "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), RELAXED_DOT_ADDS_vextternop__)
prod "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I8_lanetype, `%`_dim(16,)),), RELAXED_DOT_ADDS_vextternop__)

;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec
rec {
Expand Down
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