Skip to content

Tighten designs #4482

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
gudeh wants to merge 7 commits into
base: master
Choose a base branch
from
Open

Tighten designs #4482

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
7 commits
Select commit Hold shift + click to select a range
f8a252f
tighten initial core utilization for owned designs, also tighten cloc…
gudeh Aug 26, 2026
b6fa2ef
Merge remote-tracking branch 'private/master' into secure-owned-desig…
gudeh Aug 27, 2026
a489436
update OR
gudeh Aug 27, 2026
377fc7e
update OR
gudeh Aug 27, 2026
262afba
Update OK metrics
gudeh Aug 27, 2026
0547ebb
update OR
gudeh Sep 3, 2026
5f4b324
Merge remote-tracking branch 'private/master' into secure-owned-desig…
gudeh Sep 3, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
7 changes: 2 additions & 5 deletions flow/designs/gf12/tinyRocket/config.mk
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -25,11 +25,8 @@ export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1rf_lg6_w32_all_ffpg_sigcmin_0p
export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1rf_lg6_w32_all.gds2 \
$(PLATFORM_DIR)/gds/gf12_1rf_lg6_w32_byte.gds2

# These values must be multiples of placement site
export DIE_AREA = 0 0 400.008 399.84
export CORE_AREA = 19.992 20.16 380.016 380.16

export PLACE_DENSITY = 0.20
export CORE_UTILIZATION = 50
export PLACE_DENSITY_LB_ADDON = 0.10
Comment on lines +28 to +29

@gemini-code-assist gemini-code-assist Bot Aug 27, 2026

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

high

Using dynamic CORE_UTILIZATION instead of fixed DIE_AREA and CORE_AREA is highly risky for designs containing macros (such as the SRAMs specified in WRAP_LEFS). In physical design flows, dynamic floorplan sizing based on standard cell area changes the die boundaries whenever the netlist size fluctuates. This will break manual macro placement configurations that rely on absolute coordinates, leading to placement failures or overlaps. It is recommended to retain fixed DIE_AREA and CORE_AREA dimensions for designs with macros to ensure stability.

# These values must be multiples of placement site
export DIE_AREA    = 0 0 400.008 399.84
export CORE_AREA   = 19.992 20.16 380.016 380.16

export PLACE_DENSITY = 0.20

@gudeh gudeh Aug 28, 2026

Copy link
Copy Markdown
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Is this true @eder-matheus ?

@eder-matheus eder-matheus Aug 28, 2026

Copy link
Copy Markdown
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I'm pretty sure we have other designs with macros that uses CORE_UTILIZATION. You can double check it, but I think this is just gemini hallucinating.

@gudeh gudeh Aug 29, 2026

Copy link
Copy Markdown
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@AcKoucher @joaomai what do you say?

@AcKoucher AcKoucher Aug 31, 2026

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Your changes are fine. If a certain design were to use manual macro placement we could treat it as an exception. It's just Gemini being overly defensive.

@gudeh gudeh Aug 31, 2026

Copy link
Copy Markdown
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thanks guys!


export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl

Expand Down
2 changes: 1 addition & 1 deletion flow/designs/gf12/tinyRocket/constraint.sdc
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
set clk_name core_clock
set clk_port_name clock
set clk_period 800
set clk_period 700

@eder-matheus eder-matheus Sep 3, 2026

Copy link
Copy Markdown
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Does it change QoR at all? I don't see new metrics for this design.
Same for ihp/aes and nangate45/bp_fe.

set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
Expand Down
2 changes: 1 addition & 1 deletion flow/designs/gf180/ibex/config.mk
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ export SYNTH_HDL_FRONTEND = slang

export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

export CORE_UTILIZATION = 45
export CORE_UTILIZATION = 75
export PLACE_DENSITY_LB_ADDON = 0.1

export SWAP_ARITH_OPERATORS = 1
Expand Down
12 changes: 6 additions & 6 deletions flow/designs/gf180/ibex/rules-base.json
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -18,23 +18,23 @@
"compare": "=="
},
"placeopt__design__instance__area": {
"value": 725567,
"value": 724846,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
"value": 15783,
"value": 15301,
"compare": "<="
},
"detailedplace__design__violations": {
"value": 0,
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
"value": 1372,
"value": 1330,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
"value": 1372,
"value": 1330,
"compare": "<="
},
"cts__timing__setup__ws": {
Expand Down Expand Up @@ -62,7 +62,7 @@
"compare": ">="
},
"globalroute__timing__setup__tns": {
"value": -2.0,
"value": -8.23,
"compare": ">="
},
"globalroute__timing__hold__ws": {
Expand Down Expand Up @@ -94,7 +94,7 @@
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -2.07,
"value": -31.7,

@gemini-code-assist gemini-code-assist Bot Aug 27, 2026

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

medium

The total negative slack (finish__timing__setup__tns) has degraded significantly from -2.07 to -31.7. While some negative slack is expected when tightening the design, a TNS of -31.7 at the final stage is extremely high for the Ibex core on GF180. This indicates severe, unresolvable timing violations under the new 75% utilization target. Consider lowering the utilization target (e.g., to 65% or 70%) to allow the optimizer sufficient routing and buffering space to meet timing.

"compare": ">="
},
"finish__timing__hold__ws": {
Expand Down
2 changes: 1 addition & 1 deletion flow/designs/ihp-sg13g2/aes/config.mk
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ export PLATFORM = ihp-sg13g2
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

export CORE_UTILIZATION = 20
export CORE_UTILIZATION = 85

@gemini-code-assist gemini-code-assist Bot Aug 27, 2026

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

medium

Setting CORE_UTILIZATION to 85% is extremely aggressive for a standard cell design, especially when combined with a tighter clock period of 3ns. High utilization limits the router's ability to insert buffer trees for timing closure and clock tree synthesis, and typically leads to severe routing congestion and DRC violations. A utilization target between 60% and 70% is generally the practical upper limit for routability and timing closure in most technologies.

export CORE_UTILIZATION = 70

export CORE_ASPECT_RATIO = 1

export PLACE_DENSITY = 0.65
Expand Down
2 changes: 1 addition & 1 deletion flow/designs/ihp-sg13g2/aes/constraint.sdc
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ current_design aes_cipher_top

set clk_name clk
set clk_port_name clk
set clk_period 4.5
set clk_period 3
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
Expand Down
2 changes: 1 addition & 1 deletion flow/designs/ihp-sg13g2/riscv32i/config.mk
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.

export USE_FILL = 1

export CORE_UTILIZATION = 35
export CORE_UTILIZATION = 75
export PLACE_DENSITY_LB_ADDON = 0.2
export TNS_END_PERCENT = 100
export CTS_BUF_DISTANCE = 60
Expand Down
14 changes: 7 additions & 7 deletions flow/designs/ihp-sg13g2/riscv32i/rules-base.json
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,31 +10,31 @@
"level": "warning"
},
"synth__design__instance__area__stdcell": {
"value": 140000.0,
"value": 139000.0,
"compare": "<="
},
"constraints__clocks__count": {
"value": 2,
"compare": "=="
},
"placeopt__design__instance__area": {
"value": 157813,
"value": 156855,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
"value": 10692,
"value": 10640,
"compare": "<="
},
"detailedplace__design__violations": {
"value": 0,
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
"value": 930,
"value": 925,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
"value": 930,
"value": 925,
"compare": "<="
},
"cts__timing__setup__ws": {
Expand Down Expand Up @@ -74,7 +74,7 @@
"compare": ">="
},
"detailedroute__route__wirelength": {
"value": 456338,
"value": 575080,

@gemini-code-assist gemini-code-assist Bot Aug 27, 2026

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

medium

The detailed routing wirelength (detailedroute__route__wirelength) increased by approximately 26% (from 456338 to 575080), even though the standard cell area decreased slightly. This disproportionate increase in wirelength is a clear symptom of severe routing congestion caused by raising the core utilization from 35% to 75%. High congestion and excessive routing detours can lead to increased dynamic power, crosstalk, and potential DRC violations. Consider a more moderate utilization target (e.g., 60%) to balance density and routing efficiency.

"compare": "<="
},
"detailedroute__route__drc_errors": {
Expand Down Expand Up @@ -106,7 +106,7 @@
"compare": ">="
},
"finish__design__instance__area": {
"value": 168206,
"value": 167407,
"compare": "<="
}
}
6 changes: 3 additions & 3 deletions flow/designs/nangate45/bp_fe_top/config.mk
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -16,15 +16,15 @@ export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram45_512x64.lib \
$(PLATFORM_DIR)/lib/fakeram45_64x7.lib \
$(PLATFORM_DIR)/lib/fakeram45_64x96.lib

export DIE_AREA = 0 0 800 600
export CORE_AREA = 10 10 790 590

export CORE_UTILIZATION = 50
export PLACE_DENSITY_LB_ADDON = 0.11
Comment on lines +20 to +21

@gemini-code-assist gemini-code-assist Bot Aug 27, 2026

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

high

Removing the fixed DIE_AREA and CORE_AREA in favor of dynamic CORE_UTILIZATION is problematic for bp_fe_top because it contains multiple SRAM macros (ADDITIONAL_LEFS). Dynamic floorplan sizing causes the die/core boundaries to shift whenever the synthesized netlist size changes. This invalidates manual macro placement configurations (typically defined with absolute coordinates), leading to out-of-bounds or overlapping macro placement errors. To tighten the design safely, calculate and specify a smaller, fixed DIE_AREA and CORE_AREA instead of using dynamic utilization.

export DIE_AREA    = 0 0 800 600 
export CORE_AREA   = 10 10 790 590 

export PLACE_DENSITY_LB_ADDON = 0.11


export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/io.tcl


export MACRO_PLACE_HALO = 10 10

export PLACE_DENSITY_LB_ADDON = 0.11
export TNS_END_PERCENT = 100

export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/fastroute.tcl
Expand Down
2 changes: 1 addition & 1 deletion tools/OpenROAD
Open in desktop
Submodule OpenROAD updated 5 files
+1 −0 .bazelrc
+4 −2 MODULE.bazel
+3,437 −3,469 MODULE.bazel.lock
+2 −0 test/downstream/.bazelrc
+4 −1 test/downstream/MODULE.bazel