Opt in first 8 designs to use 'syn' #4270
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This pull request introduces a new synthesis flow option (SYNTH_USE_SYN) that utilizes the built-in OpenROAD 'syn' tool via a new synth_syn.tcl script, updating the Makefile, metrics extraction, and various design configurations to support it. The code review feedback highlights several critical improvements for robustness: adding missing Verilog and SDC dependencies to the Makefile target to prevent breaking incremental builds, guarding environment variables (DONT_USE_CELLS and SYNTH_SLANG_ARGS) against Tcl runtime errors when undefined, and keeping vIdirsArgs as a proper Tcl list to safely handle paths with special characters.
| ifeq ($(SYNTH_USE_SYN),1) | ||
| $(eval $(call do-step,1_synth,$(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(LIB_FILES),synth_syn)) | ||
| else | ||
| $(eval $(call do-step,1_synth,$(RESULTS_DIR)/1_2_yosys.v $(RESULTS_DIR)/1_2_yosys.sdc $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(LIB_FILES),synth_odb)) | ||
| endif |
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In the new syn synthesis flow (SYNTH_USE_SYN=1), the 1_synth target does not list $(VERILOG_FILES) or $(SDC_FILE) as dependencies. This breaks incremental builds, as modifying any Verilog source files or timing constraints will not trigger a re-synthesis of the design. Please add them to the dependency list.
ifeq ($(SYNTH_USE_SYN),1)
$(eval $(call do-step,1_synth,$(VERILOG_FILES) $(SDC_FILE) $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(LIB_FILES),synth_syn))
else
$(eval $(call do-step,1_synth,$(RESULTS_DIR)/1_2_yosys.v $(RESULTS_DIR)/1_2_yosys.sdc $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(LIB_FILES),synth_odb))
endif
| read_lef $lef | ||
| } | ||
| } | ||
| set_dont_use $::env(DONT_USE_CELLS) |
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The environment variable DONT_USE_CELLS is not marked as required and does not have a default value in variables.json. If it is not defined in the environment, accessing $::env(DONT_USE_CELLS) directly will throw a Tcl runtime error and crash the synthesis flow. Please guard this call using env_var_exists_and_non_empty.
if { [env_var_exists_and_non_empty DONT_USE_CELLS] } {
set_dont_use $::env(DONT_USE_CELLS)
}
| set vIdirsArgs "" | ||
| if { [env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS] } { | ||
| foreach dir $::env(VERILOG_INCLUDE_DIRS) { | ||
| lappend vIdirsArgs "-I$dir" | ||
| } | ||
| set vIdirsArgs [join $vIdirsArgs] | ||
| } |
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Instead of joining the vIdirsArgs list into a space-separated string and then using expansion ({*}) to split it back, it is cleaner and safer to keep vIdirsArgs as a proper Tcl list. This avoids potential issues with paths containing special characters or spaces.
set vIdirsArgs [list]
if { [env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS] } {
foreach dir $::env(VERILOG_INCLUDE_DIRS) {
lappend vIdirsArgs "-I$dir"
}
}
| } | ||
| } | ||
|
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| lappend elaborate_args {*}$::env(SYNTH_SLANG_ARGS) |
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Signed-off-by: Martin Povišer <povik@cutebit.org>
Signed-off-by: Martin Povišer <povik@cutebit.org>
Signed-off-by: Martin Povišer <povik@cutebit.org>
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