QSPI_XIP_CTRL: Fix missing default assignment for HREADYOUT in st_rw state

[ashnaaseth2325-oss]

1. SUMMARY

This PR fixes a missing default assignment for HREADYOUT in the st_rw state, which could cause it to hold a stale value. The change ensures correct ready signaling when no active transfer is present.
Primary changes are in flow/designs/src/chameleon/IPs/QSPI_XIP_CTRL.v within the QSPI_XIP_CTRL module.

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2. FIX

// Before
else if(HTRANS[1] & HSEL & HREADY & ~c_hit) HREADYOUT <= 1'b0;
// else HREADYOUT <= 1'b1;

// After
else if(HTRANS[1] & HSEL & HREADY & ~c_hit) HREADYOUT <= 1'b0;
else HREADYOUT <= 1'b1;

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3. VERIFICATION

Simulated AHB transactions covering hit, miss, and idle conditions in st_rw. Previously, HREADYOUT could remain low after a stall; after the fix, it correctly returns to 1 when no transfer is active. Behavior is now consistent with protocol expectations and other FSM states.

[gemini-code-assist]

Code Review

This pull request uncomments an assignment for the HREADYOUT signal in the st_rw state of the QSPI_XIP_CTRL module. The reviewer suggests adding a default case to the case statement to ensure HREADYOUT is driven to a safe state (1'b1) in the event of an undefined state, which prevents potential bus stalls.

[gemini-code-assist]

The case (state) statement (starting at line 90) is missing a default branch. Although the FSM state transitions are handled by a default value for nstate, the HREADYOUT signal is assigned within a clocked case block. It is a best practice in RTL design to include a default case for all control logic to ensure that signals are driven to a known safe state if the state register ever enters an undefined value (e.g., due to a glitch or SEU). For an AHB-Lite slave, the safe state for HREADYOUT is typically 1'b1 to prevent a permanent bus stall.

                            else HREADYOUT <= 1'b1;
                default :   HREADYOUT <= 1'b1;