linux: How_to_Guides: Add instructions to enable SSC on DSS PLLs #529

bluehyperX · 2025-11-24T06:55:46Z

Add information on spread spectrum clocking (SSC) and how to enable it for DSS PLLs as a How_to_Guide.

cshilwant · 2025-11-24T07:17:49Z

source/linux/Foundational_Components/Kernel/Kernel_Drivers/Display/DSS7.rst

 Documentation for tidss device tree node and its properties can be found in linux kernel device tree bindings in below directory
 ``Documentation/devicetree/bindings/display/ti/``. Seperate binding files are present for different version of the DSS controller.

+For information about configuring Spread Spectrum Clocking (SSC) for DSS, see <../../../../How_to_Guides/Target/How_to_enable_SSC_for_DSS.html>`__


use :ref: for cross referencing [0]
eg - checkout [1]

[0] - https://www.sphinx-doc.org/en/master/usage/referencing.html#role-ref

[1] - https://github.com/TexasInstruments/processor-sdk-doc/blob/master/source/linux/Foundational_Components/U-Boot/UG-DFU.rst?plain=1#L36

cshilwant · 2025-11-24T07:18:34Z

source/linux/How_to_Guides/Target/How_to_enable_SSC_for_DSS.rst

+This guide shows how to configure SSC for DSS pixel clocks on supported TI SoCs.
+
+.. important::
+   The pixel clock frequency for DPI from the DSS PLL must not exceed 165MHz. Center spread adds a 20% overshoot to the modulation depth. Account for this when you calculate the maximum frequency.


Make sure that the directive and the content block have 1 new line between them and that the content block has at least 1 newline after it.

https://github.com/TexasInstruments/processor-sdk-doc/blob/master/CONTRIBUTING.md#indentation-and-whitespace

source/linux/How_to_Guides/Target/How_to_enable_SSC_for_DSS.rst

devarsht · 2025-11-24T08:38:12Z

configs/AM62AX/AM62AX_linux_toc.txt

 linux/How_to_Guides/Target/How_to_enable_DT_overlays_in_linux
 linux/How_to_Guides/Target/How_To_Enable_M2CC3301_in_linux
 linux/How_to_Guides/Target/How_to_playback_audio_over_HDMI
+linux/How_to_Guides/Target/How_to_enable_SSC_for_DSS


Do we need a similar guide for AM62L as well?

The SSC support MR was limited to AM62x, AM62Ax, AM62Px, and AM62Dx; therefore, I have included support solely for these devices.

devarsht · 2025-11-24T08:44:21Z

source/linux/How_to_Guides/Target/How_to_enable_SSC_for_DSS.rst

+Introduction
+------------
+
+Spread Spectrum Clocking (SSC) reduces electromagnetic interference (EMI). It modulates the clock frequency. SSC varies the frequency over time. This spreads energy across many frequencies. This reduces peak emissions.


Spread Spectrum Clocking (SSC) is an EMI reduction technique that:

Modulates the clock frequency rather than keeping it constant Varies the frequency over time in a controlled manner Spreads energy across multiple frequencies instead of concentrating it at a single frequency Reduces peak emissions by distributing the electromagnetic energy

This is a common technique used in electronic systems, particularly in high-speed digital circuits, to help meet EMI compliance requirements without requiring additional shielding or filtering components.

devarsht · 2025-11-24T08:50:51Z

source/linux/How_to_Guides/Target/How_to_enable_SSC_for_DSS.rst

+
+Spread Spectrum Clocking (SSC) reduces electromagnetic interference (EMI). It modulates the clock frequency. SSC varies the frequency over time. This spreads energy across many frequencies. This reduces peak emissions.
+
+Digital clock signals are periodic and square-shaped. Most energy focuses at the center frequency and odd harmonics. SSC spreads this energy across a wider range. This reduces the peak amplitude. SSC adds jitter to the clock signal. The voltage amplitude stays unchanged.


These look like single points and not paragraph.
Most of the energy is focused at the center frequency and odd harmonics, SSC redistributes this energy across a wider range by adding a jitter to clock signal thus reducing the peak amplitude.

The voltage amplitude stays unchanged -> Do you mean to say that average amplitude stays the same?

devarsht · 2025-11-24T09:03:04Z

source/linux/How_to_Guides/Target/How_to_enable_SSC_for_DSS.rst

+.. code-block:: dts
+
+   &dss0 {
+       assigned-clocks = <&k3_clks 186 2>;


The SSC is only for output DPI clock and not for functional clock ?

SSC is applicable only to input clocks or multiplexed input clocks because these clocks are derived from PLLs that support SSC

devarsht · 2025-11-24T09:04:56Z

source/linux/How_to_Guides/Target/How_to_enable_SSC_for_DSS.rst

+- ``assigned-clock-sscs``: Configures SSC with 100 kHz modulation, 0.1% depth, center spread mode (1)
+
+.. warning::
+   This example uses center spread mode (1). Center spread has a 20% overshoot on the modulation depth. For 0.1% nominal depth, the actual peak deviation is about 0.12%.


Center spread has a 20% overshoot on the modulation depth. -> Is this documented somewhere?

For 0.1% nominal depth, the actual peak deviation is about 0.12% -> Is this documented somewhere?

Yes, this is documented in the “ AM62x, AM62Ax, AM62Px, AM62Lx Spread-Spectrum Clocking” application note by Hardware Apps team

devarsht · 2025-11-24T09:05:50Z

source/linux/How_to_Guides/Target/How_to_enable_SSC_for_DSS.rst

+
+   When using center spread:
+
+   1. Ensure the display panel can handle the higher peak frequency


How to estimate highest peak frequency as per current modulation params?

devarsht · 2025-11-24T09:10:45Z

source/linux/How_to_Guides/Target/How_to_enable_SSC_for_DSS.rst

+Display artifacts
+^^^^^^^^^^^^^^^^^
+
+If you observe display artifacts, flickering, or other visual anomalies after enabling SSC:


Do we have some data on any observed side effects after going above X modulation ?

Also did we do some internal testing with refresh rate logs enabled to see if any jitter in refresh rate with suggested/example params showed in this doc ?

You can test that with kmstest --flip.

There were no side-effects of this change. Here are the logs of kmstest -
SSC_kmstest.txt

devarsht · 2025-11-24T09:12:45Z

source/linux/How_to_Guides/Target/How_to_enable_SSC_for_DSS.rst

+
+   **You assume all responsibility for the configuration and usage of spread-spectrum clocking.** You must:
+
+   1. Research the clock limitations associated with your selected display panel


what about HDMI monitors?

HDMI works well. Here are the logs for the same -

root@am62pxx-evm:~# systemctl stop emptty root@am62pxx-evm:~# kmstest --flip Connector 0/@41: HDMI-A-1 Crtc 0/@39: 1920x1080@59.93 138.500 1920/48/32/80/+ 1080/3/5/23/- 60 (59.93) P|D Plane 0/@32: 0,0-1920x1080 Fb 52 1920x1080-XR24 press enter to exit Connector 0: fps 60.00, slowest 16.70 ms Connector 0: fps 59.93, slowest 16.70 ms Connector 0: fps 59.93, slowest 16.72 ms Connector 0: fps 59.93, slowest 16.77 ms

StaticRocket

Commit tag: https://github.com/TexasInstruments/processor-sdk-doc/blob/master/CONTRIBUTING.md#commit-types

source/linux/How_to_Guides/Target/How_to_enable_SSC_for_DSS.rst

StaticRocket

Very nice

cshilwant · 2025-12-04T20:42:35Z

The PR looks good to me now.
Will wait for @devarsht to re-review

devarsht · 2025-12-09T11:06:17Z

source/linux/How_to_Guides/Target/How_to_enable_SSC_for_DSS.rst

+.. important::
+
+   The pixel clock frequency for DPI from the DSS PLL must not exceed 165MHz. When using center spread mode, calculate the highest peak frequency to ensure it stays under this limit:
+


you mean to say highest frequency should stay under 165Mhz?

Here nominal frequency is the target pixel clock ?
I think we do require 165 Mhz for say 1920x1200 resolution ? So isn't it possible to set nominal frequency as 165 Mhz in this case?

The highest frequency should be equal to 165Mhz or below 165Mhz. If 165Mhz is required then, user must use down spread mode instead of center spread mode to avoid exceeding the nominal frequency.

Documentation for reference - https://www.ti.com/lit/pdf/spradk1

What about DSI and OLDI PLLs ? There the frequency is required is more. for e.g. OLDI uses 7x the frequency. For DSI too we support higher resolutions so max is 300 Mhz. Are you sure this is a limitation ?

also @bluehyperX, please add the reference for appnote and mention it somewhere to refer to it for further guidance.

Fixed and updated the references as well

devarsht · 2025-12-11T11:14:35Z

source/linux/How_to_Guides/Target/How_to_enable_SSC_for_DSS.rst

+
+Digital clock signals have a square wave shape. Most energy focuses at the center frequency and odd harmonics. In the frequency domain, SSC reduces the peak amplitude of the digital clock signal by spreading the energy across a wider frequency range. In the time domain, SSC adds jitter to the clock signal, but the voltage amplitude remains unchanged.
+
+Display Subsystem (DSS) supports SSC configuration for its pixel clocks through device tree properties. This helps you meet EMI compliance requirements. For DPI, DSS typically uses Phase-Locked Loop (PLL) 17. You can also use PLL 16 or PLL 18.


Let's not use PLL 16, PLL 18, PLL 17 naming. Moreover PLL 18 is not present for all SoCs as wel.

Let's remove below:
For DPI, DSS typically uses Phase-Locked Loop (PLL) 17. You can also use PLL 16 or PLL 18.

And keep below instead:

The Display Subsystem (DSS) supports Spread Spectrum Clocking (SSC) configuration for its pixel clock sources. These pixel clocks feed the DSS video ports, which can operate in two modes:

Direct mode: Video ports output DPI signals directly to the SoC pins, which can then be connected externally to an HDMI bridge or directly to a DPI panel

Bridge mode: Video ports connect to internal OLDI or DSI bridge controllers, which then drive external display panels

I have removed all the mention of PLL from the docs as I feel it was not required to explain what SSC is and how to enable it for Display pixel clocks. I have simplified the documentation on only discuss about SSC and added reference to the DSS documentation if someone needs to know more about how DSS works.

devarsht · 2025-12-11T11:23:12Z

source/linux/How_to_Guides/Target/How_to_enable_SSC_for_DSS.rst

+
+   &dss0 {
+       assigned-clocks = <&k3_clks 186 2>;
+       assigned-clock-sscs = <100000 10 1>;


Can you please also add example for enabling ssc for multiple pixel clocks ? For e.g. am62p has 2 vp clocks vp1 and vp2. How can user enable ssc for both.

devarsht · 2025-12-11T11:27:22Z

source/linux/How_to_Guides/Target/How_to_enable_SSC_for_DSS.rst

+================
+
+- SSC is currently supported only on display PLL for these SoCs: AM62x, AM62Ax, AM62Dx, AM62Px
+- The display PLL is typically PLL 17. You can also use PLL 16 or PLL 18 for DPI applications


Let's remove this line. It is not applicable for all SoCs. Maybe you can mention as below:

SSC is typically required for PLLs driving video ports that output DPI signals directly to SoC pins. However, SSC can also optionally be enabled for video ports connected to internal bridges (OLDI or DSI).

Removed this line completely.

If support is not available for all devices (so only 62x, 62a, 62d, 62p), utilize .. ifconfig:: to state where SSC is supported.

ex: .. ifconfig:: CONFIG_part_family in ('AM62PX_family')

I have removed the list of SoC names from the statement. This How-To-Guide is only available for 62x, 62a, 62d, and 62p, so stating the SoC names again in the document was not needed.

Add comprehensive how-to guide for enabling Spread Spectrum Clocking (SSC) on Display Subsystem (DSS) Phase-locked loops (PLLs). The guide covers: - SSC configuration parameters via device tree - Three configuration examples (center spread, down spread, greater depth) - Supported SoCs: AM62x, AM62Ax, AM62Dx, AM62Px - Troubleshooting and best practices - Customer responsibilities Signed-off-by: Sparsh Kumar <sparsh-kumar@ti.com>

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		Spread Spectrum Clocking (SSC) reduces electromagnetic interference (EMI). It modulates the clock frequency. SSC varies the frequency over time. This spreads energy across many frequencies. This reduces peak emissions.

		Digital clock signals are periodic and square-shaped. Most energy focuses at the center frequency and odd harmonics. SSC spreads this energy across a wider range. This reduces the peak amplitude. SSC adds jitter to the clock signal. The voltage amplitude stays unchanged.


		When using center spread:

		1. Ensure the display panel can handle the higher peak frequency


		You assume all responsibility for the configuration and usage of spread-spectrum clocking. You must:

		1. Research the clock limitations associated with your selected display panel

		.. important::

		The pixel clock frequency for DPI from the DSS PLL must not exceed 165MHz. When using center spread mode, calculate the highest peak frequency to ensure it stays under this limit:


		Digital clock signals have a square wave shape. Most energy focuses at the center frequency and odd harmonics. In the frequency domain, SSC reduces the peak amplitude of the digital clock signal by spreading the energy across a wider frequency range. In the time domain, SSC adds jitter to the clock signal, but the voltage amplitude remains unchanged.

		Display Subsystem (DSS) supports SSC configuration for its pixel clocks through device tree properties. This helps you meet EMI compliance requirements. For DPI, DSS typically uses Phase-Locked Loop (PLL) 17. You can also use PLL 16 or PLL 18.

linux: How_to_Guides: Add instructions to enable SSC on DSS PLLs #529

Are you sure you want to change the base?

linux: How_to_Guides: Add instructions to enable SSC on DSS PLLs #529

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