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The project aiming to simulate a custom designed architecture in Verilog in the extent of CENG 3010 Computer Organization course.

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_xmsgs
_xmsgs
 
 
iseconfig
iseconfig
 
 
isim
isim
 
 
ALU.v
ALU.v
 
 
ALU_beh.prj
ALU_beh.prj
 
 
ALU_stx_beh.prj
ALU_stx_beh.prj
 
 
ALU_summary.html
ALU_summary.html
 
 
LCD.v
LCD.v
 
 
Processor_Design.gise
Processor_Design.gise
 
 
Processor_Design.xise
Processor_Design.xise
 
 
README.md
README.md
 
 
control_unit.v
control_unit.v
 
 
data_memory.v
data_memory.v
 
 
fuse.xmsgs
fuse.xmsgs
 
 
fuseRelaunch.cmd
fuseRelaunch.cmd
 
 
instruction_memory.v
instruction_memory.v
 
 
isim.cmd
isim.cmd
 
 
processor.cmd_log
processor.cmd_log
 
 
processor.prj
processor.prj
 
 
processor.v
processor.v
 
 
processor.xst
processor.xst
 
 
processor_isim_beh.exe
processor_isim_beh.exe
 
 
processor_summary.html
processor_summary.html
 
 
processor_tb.v
processor_tb.v
 
 
processor_tb_beh.prj
processor_tb_beh.prj
 
 
processor_tb_isim_beh.exe
processor_tb_isim_beh.exe
 
 
processor_tb_isim_beh.wdb
processor_tb_isim_beh.wdb
 
 
processor_tb_stx_beh.prj
processor_tb_stx_beh.prj
 
 
register_file.v
register_file.v
 
 
webtalk_pn.xml
webtalk_pn.xml
 
 
xilinxsim.ini
xilinxsim.ini
 
 

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Processor-Verilog-Simulation

This project is implemented in the extent of CENG 3010 Computer Organization as a part of the term project 2. The other part of the project can be found here, and further details can be found here.

About

The project aiming to simulate a custom designed architecture in Verilog in the extent of CENG 3010 Computer Organization course.

Resources

Readme
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