Instruction pipeline rewrite - #53
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…ions of the components and composites in the demo
… for a hypothetical playable component
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…posite!` macro; added generated syntax resolution traits for composites
…rogramCounter` from the `Instruction` trait; added support for resolving and loading parsed modules
…ecode loading (keeping the bytecode container for planned codegen)
…ime instruction, value, and type resolution explicit (components now define syntax of their instructions, and resolution belongs to the composite
…e vihaco rewrite; moved `component!`'s `instruction` block into a `runtime` block; updated docs
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Contents (outside of implementation):
demos/examplescontains the demo described indemos/examples/demo.md. This contains the two CPU example running withsend/recvand a global clock that is executing events in a sorted heap. Read this first for what the rewrite will look like in a working machine,demos/examples/democontains the contents organized logically based on framework level, stdlib level, and author level conceptsdemos/examples/demo-vihaco-concepts.mdcontains the concepts at the vihaco level, including what the instruction pipeline will look like, along with some (really) simple examples. It also contains a table that maps the new concepts onto those that already exist within vihaco, as well as some of the macros that will generate the content marked "generated" throughout the demovisioncontains all of the planning documents that went into the vihaco rewrite concepts and the clock timing spec. The documents currently in there describe the hope for macro generation, what types and values will look like, what resolution will look like, etc. when they are ported to the rewrite